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    APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE
    61.
    发明申请
    APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE 有权
    执行第二个架构计算机上第一个计算机体系结构的程序的设备

    公开(公告)号：US20120144167A1

    公开(公告)日：2012-06-07

    申请号：US13371766

    申请日：2012-02-13

    申请人： John S. Yates, JR. ,  Matthew F. Storch ,  Sandeep Nijhawan ,  Dale R. Jurich ,  Korbin S. Van Dyke

    发明人： John S. Yates, JR. ,  Matthew F. Storch ,  Sandeep Nijhawan ,  Dale R. Jurich ,  Korbin S. Van Dyke

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/45554 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3861

    摘要： A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.

    摘要翻译： 多指令集架构（ISA）计算机系统包括计算机程序，第一处理器，第二处理器，轮廓仪和翻译器。 计算机程序包括第一ISA的指令，第一ISA具有第一复杂度。 第一处理器被配置为执行第一ISA的指令。 第二处理器被配置为执行第二ISA的指令，第二ISA不同于第一ISA并且具有第二复杂度，其中第二复杂度小于第一复杂度。 分析器被配置为选择用于转换为第二ISA的指令的计算机程序的块，其中该块包括第一ISA的一个或多个指令。 翻译器被配置为将第一ISA的块转换为第二ISA的指令以供第二处理器执行。

    Radial temperature control for lattice-mismatched epitaxy
    63.
    发明申请
    Radial temperature control for lattice-mismatched epitaxy 失效
    晶格失配外延的径向温度控制

    公开(公告)号：US20070259535A1

    公开(公告)日：2007-11-08

    申请号：US11418634

    申请日：2006-05-05

    申请人： Lori Washington ,  Sandeep Nijhawan ,  David Carlson

    发明人： Lori Washington ,  Sandeep Nijhawan ,  David Carlson

    IPC分类号： H01L21/31

    CPC分类号： C30B25/12 ,  C30B25/02 ,  C30B25/10 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007

    摘要： Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the susceptor in thermal communication with the substrate. A group-III precursor and a nitrogen precursor are flowed into the processing chamber. The susceptor is heated with a nonuniform temperature profile to heat the substrate. A nitride layer is deposited over the heated substrate with a thermal chemical vapor deposition process within the processing chamber using the group-III precursor and the nitrogen precursor.

    摘要翻译： 公开了制造复合氮化物半导体结构的方法。 基板设置在处理室中的基座上方，基座与基板热连通。 III族前体和氮前体流入处理室。 感受器以不均匀的温度分布被加热以加热基底。 使用III族前体和氮前体，在处理室内利用热化学气相沉积工艺在加热的衬底上沉积氮化物层。

    Buffer-layer treatment of MOCVD-grown nitride structures
    64.
    发明申请
    Buffer-layer treatment of MOCVD-grown nitride structures 失效
    MOCVD生长氮化物结构的缓冲层处理

    公开(公告)号：US20070254458A1

    公开(公告)日：2007-11-01

    申请号：US11414012

    申请日：2006-04-27

    申请人： David Bour ,  Jacob Smith ,  Sandeep Nijhawan

    发明人： David Bour ,  Jacob Smith ,  Sandeep Nijhawan

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02513 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262

    摘要： Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the amorphous buffer layer coalesces into crystallites over the substrate. The substrate is exposed to a corrosive agent to destroy at least some of the crystallites. A crystalline nitride layer is formed over the substrate at a third temperature using the crystallites remaining after exposure to the corrosive agent as seed crystals. The third temperature is greater than the first temperature. The crystalline nitride layer also includes nitrogen and a group-III element.

    摘要翻译： 公开了用于制造复合氮化物半导体结构的方法。 在第一温度下，在设置在基板处理室内的基板上形成包含氮和III族元素的非晶缓冲层。 室内的温度增加到非晶缓冲层在衬底上聚结成微晶的第二温度。 将基底暴露于腐蚀剂以破坏至少一些微晶。 在第三温度下使用在作为晶种暴露于腐蚀剂之后残留的微晶，在衬底上形成结晶氮化物层。 第三温度大于第一温度。 结晶氮化物层还包括氮和III族元素。

    Index-Matched Insulators
    67.
    发明申请
    Index-Matched Insulators 有权
    指数匹配绝缘子

    公开(公告)号：US20140034957A1

    公开(公告)日：2014-02-06

    申请号：US13648786

    申请日：2012-10-10

    申请人： Philip Kraus ,  Minh-Huu Le ,  Sandeep Nijhawan

    发明人： Philip Kraus ,  Minh-Huu Le ,  Sandeep Nijhawan

    IPC分类号： H01L33/32 ,  H01L31/0232

    CPC分类号： H01L31/02167 ,  H01L31/02161 ,  H01L33/44 ,  Y02E10/50

    摘要： Devices are described including a first component and a second component, wherein the first component comprises a Group III-N semiconductor and the second component comprises a bimetallic oxide containing tin, having an index of refraction within 15% of the index of refraction of the Group III-N semiconductor, and having negligible extinction coefficient at wavelengths of light emitted or absorbed by the Group III-N semiconductor. The first component is in optical contact with the second component. Exemplary bimetallic oxides include Sn1-xBixO2 where x≅0.10, Zn2SnO2, Sn1-xAlxO2 where x≅0.18, and Sn1-xMgxO2 where x≅0.16. Methods of making and using the devices are also described.

    摘要翻译： 描述了包括第一部件和第二部件的装置，其中第一部件包括III-N族半导体，第二部件包括含锡的双金属氧化物，折射率在该组折射率的15％以内 III-N半导体，并且在由III-N族半导体发射或吸收的光的波长处具有可忽略的消光系数。 第一部件与第二部件光学接触。 示例性双金属氧化物包括Sn1-xBixO2，其中x0.10，Zn2SnO2，Sn1-xAlxO2，其中x≅0.18，Sn1-xMgxO2，其中x≅0.16。 还描述了制造和使用装置的方法。

    Dislocation-specific lateral epitaxial overgrowth to reduce dislocation density of nitride films
    69.
    发明授权
    Dislocation-specific lateral epitaxial overgrowth to reduce dislocation density of nitride films 失效
    位错特异性侧向外延生长以减少氮化物膜的位错密度

    公开(公告)号：US07560364B2

    公开(公告)日：2009-07-14

    申请号：US11429084

    申请日：2006-05-05

    申请人： David Bour ,  Sandeep Nijhawan ,  Jacob Smith ,  Lori Washington

    发明人： David Bour ,  Sandeep Nijhawan ,  Jacob Smith ,  Lori Washington

    IPC分类号： H01L21/20

    CPC分类号： C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/025

    摘要： In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

    摘要翻译： 根据本发明，提供了用于降低氮化物外延膜的位错密度的改进方法。 具体地，提供了原位蚀刻处理以优先蚀刻氮化物外延层的位错，以防止通过氮化物外延层的位错穿透。 在蚀刻位错之后，进行外延层过度生长。 在某些实施例中，位错的蚀刻与外延层的生长同时发生。 在其它实施例中，在外延层过度生长之前，在形成于位错处的蚀刻坑内沉积电介质掩模。