公开(公告)号：US4571815A

公开(公告)日：1986-02-25

申请号：US650315

申请日：1984-09-12

申请人： Bantval J. Baliga ,  Robert P. Love

发明人： Bantval J. Baliga ,  Robert P. Love

IPC分类号： H01L21/332 ,  H01L21/335 ,  H01L21/74 ,  H01L29/10 ,  H01L21/38

CPC分类号： H01L29/66363 ,  H01L21/743 ,  H01L29/1066 ,  H01L29/66416

摘要： A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.

摘要翻译： 垂直沟道结栅电场控制装置（例如，场效应晶体管或场控晶闸管）包括半导体基区域层和形成在基区域层的上表面中的具有垂直壁的多个沟槽。 在基底区域层的上表面上的凹槽之间但不延伸到沟槽的是上电极区域，例如源电极区域或阴极电极区域。 形成在凹槽底部和侧壁中的是结栅区域。 上电极端子金属化通常在上部器件层上蒸发，并且栅极端子金属化在沟槽底部的结栅区域之上。 因此，所公开的结构沿着用于低电阻栅极连接的凹入栅极区域具有连续的金属化。 该结构有利于通过还公开的方法制造，其避免了掩模中限定源极（或阴极）和栅极区域的位置的任何关键的光刻对准步骤，并且避免了在形成电极时需要用于金属界定的任何掩模或掩模对准 金属化。 作为上电极和栅极区域的结构的结果，避免在槽侧壁上的任何金属沉积是关键的。

公开(公告)号：US5637898A

公开(公告)日：1997-06-10

申请号：US577859

申请日：1995-12-22

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/42368 ,  H01L29/0878 ,  H01L29/7813

摘要： A power transistor having high breakdown voltage and low on-state resistance includes a vertical field effect transistor in a semiconductor substrate having a plurality of source, channel, drift and drain regions therein. A trench having a bottom in the drift region and opposing sidewalls which extend adjacent the drift, channel and source regions is also provided in the substrate, at a face thereof. The trench preferably includes an insulated gate electrode therein for modulating the conductivity of the channel and drift regions in response to the application of a turn-on gate bias. The insulated gate electrode includes an electrically conductive gate in the trench and an insulating region which lines a sidewall of the trench adjacent the channel and drift regions. The insulating region has a nonuniform cross-sectional area between the trench sidewall and the gate which enhances the forward voltage blocking capability of the transistor by inhibiting the occurrence of high electric field crowding at the bottom of the trench. The thickness of the insulating region is preferably greater than 1500 .ANG. along the portion of the sidewall which extends adjacent the drift region and less than 750 .ANG. along the portion of the sidewall which extends adjacent the channel region. To provide low on-state resistance, the drift region is also nonuniformly doped to have a linearly graded doping profile which decreases from greater than about 1.times.10.sup.17 cm.sup.-3 to less than about 5.times.10.sup.-16 cm.sup.-3 in a direction from the drain region to the channel region.

摘要翻译： 具有高击穿电压和低导通电阻的功率晶体管包括在其中具有多个源极，沟道，漂移和漏极区域的半导体衬底中的垂直场效应晶体管。 在衬底的表面上还设置有在漂移区域中具有底部的沟槽和在漂移，沟道和源极区域附近延伸的相对的侧壁。 沟槽优选地包括其中的绝缘栅电极，用于响应于施加导通栅极偏压而调制沟道和漂移区的导电性。 绝缘栅电极包括在沟槽中的导电栅极以及绝缘区域，其中沟槽的侧壁与沟道和漂移区相邻。 绝缘区域在沟槽侧壁和栅极之间具有不均匀的横截面积，其通过抑制沟槽底部的高电场拥挤的发生而增强了晶体管的正向电压阻断能力。 绝缘区域的厚度优选大于沿着邻近漂移区域延伸的侧壁部分的1500，而沿邻近沟道区域延伸的侧壁部分小于750。 为了提供低导通电阻，漂移区也被不均匀地掺杂以具有线性渐变的掺杂分布，其从从漏极区到低于约5×10 16 cm -3的方向从大于约1×10 17 cm -3减小到小于约5×10 16 cm -3 通道区域。

公开(公告)号：US5449925A

公开(公告)日：1995-09-12

申请号：US238228

申请日：1994-05-04

申请人： Bantval J. Baliga ,  Dev Alok

发明人： Bantval J. Baliga ,  Dev Alok

IPC分类号： H01L21/04 ,  H01L21/265 ,  H01L21/329 ,  H01L29/06 ,  H01L29/24 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L29/417 ,  H01L29/43

CPC分类号： H01L29/1608 ,  H01L29/6606 ,  H01L29/861 ,  H01L29/872 ,  Y10S438/931

摘要： Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.

摘要翻译： 耐压击穿的单晶碳化硅半导体器件通过在单晶碳化硅衬底的表面上形成与碳化硅器件相邻并围绕的非晶碳化硅终止区来获得。 优选通过以足够的能量和剂量将电惰性离子（例如氩）注入到衬底面中来形成无定形终止区域以使衬底面非晶化。 器件触点或触点用作注入掩模，以为器件提供自对准的端接区域。 端接器件可能具有接近碳化硅理想值的耐电压击穿电阻。

公开(公告)号：US5446310A

公开(公告)日：1995-08-29

申请号：US895339

申请日：1992-06-08

申请人： Bantval J. Baliga ,  Prasad Venkatraman

发明人： Bantval J. Baliga ,  Prasad Venkatraman

IPC分类号： H01L21/66 ,  H01L23/525 ,  H01L23/48

CPC分类号： H01L22/22 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An integrated circuit power device includes many cell blocks which are electrically connected in parallel, with each of the cell blocks including at least one cell such as MOSFET, electrically connected in parallel. External measurement access means such as test pads are electrically connected to each cell block, so that the cell blocks can be externally measured and a defective cell block can be identified. Externally activated disabling means such as fusible links are also provided, so that the fusible links connected to defective cell blocks can be opened. An operable integrated circuit power device is thereby obtained, notwithstanding a defective cell block. The fusible links are incapable of automatic activation in response to the defect in the cell block, but are externally opened upon detection of a defective cell block. By decoupling the defect measurement and cell disabling functions, low levels of leakage current may be specified for the power device. The fusible links are preferably formed using the same mask and material as the gate electrode, so that extra fabrication steps are not needed.

摘要翻译： 集成电路功率器件包括并联电连接的许多单元块，每个单元块包括并联电连接的至少一个诸如MOSFET的单元。 诸如测试焊盘的外部测量访问装置电连接到每个单元块，使得可以外部测量单元块，并且可以识别出有缺陷的单元块。 还提供外部激活的禁用装置，例如可熔链路，使得连接到有缺陷的单元块的可熔链路可以被打开。 由此获得可操作的集成电路功率器件，尽管电池块有故障。 熔丝链接不能响应于单元块中的缺陷而自动激活，而是在检测到有缺陷的单元块时被外部打开。 通过去除缺陷测量和电池禁用功能，可以为功率器件指定低电平的漏电流。 优选地，使用与栅极电极相同的掩模和材料形成熔断链，使得不需要额外的制造步骤。

公开(公告)号：US5436174A

公开(公告)日：1995-07-25

申请号：US008719

申请日：1993-01-25

申请人： Bantval J. Baliga ,  Dev Alok

发明人： Bantval J. Baliga ,  Dev Alok

IPC分类号： H01L21/04 ,  H01L21/76 ,  H01L21/266

CPC分类号： H01L21/7602 ,  H01L21/0475 ,  Y10S148/148 ,  Y10S438/924 ,  Y10S438/931

摘要： A trench is formed in a monocrystalline silicon carbide substrate by amorphizing a portion of the monocrystalline silicon carbide substrate to define an amorphous silicon carbide region therein. The amorphous silicon carbide region is then removed, to produce a trench in the monocrystalline silicon carbide substrate corresponding to the removed amorphous silicon carbide region. The substrate may be amorphized by implanting ions into a masked substrate so that the implanted ions convert the unmasked portions of the substrate into amorphous silicon carbide. The amorphous silicon carbide may be etched using at least one etchant which etches amorphous silicon carbide relatively quickly and etches monocrystalline silicon carbide relatively slowly, such as hydrofluoric acid and nitric acid. The amorphizing and removing steps may be repeatedly performed to form deep trenches.

摘要翻译： 通过将单晶碳化硅衬底的一部分非晶化以在其中限定非晶碳化硅区域，在单晶碳化硅衬底中形成沟槽。 然后去除非晶碳化硅区域，以在对应于去除的非晶碳化硅区域的单晶碳化硅衬底中产生沟槽。 衬底可以通过将离子注入到掩模衬底中而非晶化，使得注入的离子将衬底的未掩模部分转化为非晶碳化硅。 可以使用至少一种相当快地蚀刻非晶碳化硅的蚀刻剂来蚀刻非晶碳化硅，并相对缓慢地蚀刻单晶碳化硅，例如氢氟酸和硝酸。 可以重复进行非晶化和去除步骤以形成深沟槽。

公开(公告)号：US5396087A

公开(公告)日：1995-03-07

申请号：US990062

申请日：1992-12-14

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/74 ,  H01L23/58 ,  H01L29/76 ,  H01L31/111

CPC分类号： H01L29/0653 ,  H01L29/1095 ,  H01L29/7395 ,  H01L2924/0002

摘要： A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact. The prevention of minority carrier injection reduces the likelihood of parasitic latch-up by cutting-off the regenerative P-N-P-N path that would otherwise exist between the anode and cathode. The insulating region is selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4 and is preferably formed using SIMOX processing techniques.

摘要翻译： 无闩锁绝缘栅极晶体管包括电连接到阳极接触件的阳极区域，阳极区域上的第一基极区域，第一基极区域上的连接到阴极接触件的第二基极区域，第二基极区域上的绝缘区域 基极区域和场效应晶体管，电连接在阴极触点和第一基极区域之间。 场效应晶体管响应于导通偏置信号而在第一基极区域和阴极接触件之间提供电连接。 绝缘区域防止第二基极区域和场效应晶体管之间的导电，并且特别地抑制从第二基极区域到与阴极接触件电连接的场效应晶体管的源极的少数载流子注入。 防止少数载流子注入通过切断否则存在于阳极和阴极之间的再生P-N-P-N路径来减少寄生闩锁的可能性。 绝缘区选自SiO 2，Si 3 N 4，Al 2 O 3和MgAl 2 O 4，优选使用SIMOX处理技术形成。

公开(公告)号：US5396085A

公开(公告)日：1995-03-07

申请号：US174690

申请日：1993-12-28

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/80 ,  H01L27/085 ,  H01L29/12 ,  H01L29/24 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20

CPC分类号： H01L29/7813 ,  H01L27/085 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7832 ,  H01L29/8083 ,  H01L29/8122

摘要： A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

摘要翻译： 碳化硅切换装置包括硅和碳化硅的复合衬底中的三端互连硅MOSFET和碳化硅MESFET（或JFET）。 对于三端子操作，碳化硅MESFET的栅电极与硅MOSFET的源极区域电短路，并且碳化硅MESFET的源极区域与复合衬底中的硅MOSFET的漏极电连接。 因此，硅MOSFET的源极和栅电极以及碳化硅MESFET（或JFET）的漏极提供三端子控制。 开关器件被设计为常闭，因此当MOSFET栅电极短路到源电极时，阻塞正漏极偏置。 在低漏极偏置下，MOSFET由具有非导电硅有源区的MOSFET提供。 较高的漏极偏置由碳化硅MESFET（或JFET）中的耗尽区的形成来支持。 为了使器件导通，栅电极被正偏置，并且在硅有源区中形成具有相对低电阻的反型层通道。 该通道将碳化硅MESFET（或JFET）的源极与硅MOSFET的源电连接，从而在施加正的漏极偏压时导通该器件。

公开(公告)号：US5262668A

公开(公告)日：1993-11-16

申请号：US930147

申请日：1992-08-13

申请人： Shang-hui L. Tu ,  Bantval J. Baliga

发明人： Shang-hui L. Tu ,  Bantval J. Baliga

IPC分类号： H01L29/872 ,  H01L29/48

CPC分类号： H01L29/872 ,  H01L29/47 ,  H01L29/8725

摘要： A Schottky barrier rectifier includes regions of different Schottky barrier heights. Preferably, alternating regions of relatively high and relative low barrier heights are provided on a semiconductor substrate and are electrically connected in parallel to form a single Schottky barrier rectifier. The alternating regions may be provided by laterally spaced apart regions of a first metal on the semiconductor substrate and a layer of a second metal on the regions of the first metal and on the semiconductor substrate between the regions of first metal. Alternatively, a plurality of spaced apart barrier altering regions, such as a plurality of shallow implants, are formed in the semiconductor substrate, and a continuous metal layer is formed on the semiconductor substrate. In yet another embodiment, plurality of laterally spaced apart trenches are formed in the semiconductor substrate. First metal regions are formed at the bottom of each trench and a second metal layer is formed on the trench bottoms, trench walls and on the substrate face between the trenches. Still alternatively, a barrier height altering region, such as a shallow implant, is formed in the semiconductor substrate adjacent the trench bottoms, and a metal layer is formed on the trench bottoms, on the trench walls and on the first face between the trenches.

摘要翻译： 肖特基势垒整流器包括不同肖特基势垒高度的区域。 优选地，在半导体衬底上提供相对较高和相对较低的屏障高度的交替区域并且并联电连接以形成单个肖特基势垒整流器。 交替区域可以由半导体衬底上的第一金属的横向间隔开的区域和在第一金属的区域上的第二金属层和第一金属区域之间的半导体衬底上提供。 或者，在半导体衬底中形成多个间隔开的屏障改变区域，例如多个浅埋入物，并且在半导体衬底上形成连续的金属层。 在另一个实施例中，多个横向间隔开的沟槽形成在半导体衬底中。 第一金属区域形成在每个沟槽的底部，并且第二金属层形成在沟槽底部，沟槽壁和沟槽之间的衬底面上。 或者，在与沟槽底部相邻的半导体衬底中形成诸如浅注入的势垒高度改变区域，并且在沟槽底部，沟槽壁上和沟槽之间的第一面上形成金属层。

公开(公告)号：US5241194A

公开(公告)日：1993-08-31

申请号：US990659

申请日：1992-12-14

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/745 ,  H01L29/749

CPC分类号： H01L29/7455 ,  H01L29/749

摘要： A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias. The insulating region, on the other hand, prevents direct electrical conduction between the second base region and the source of the depletion-mode transistor. The insulating region can be formed as a buried dielectric layer during processing and is preferably selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub. 4.

摘要翻译： 具有集成的单极性门控制的基极电阻控制晶闸管包括具有阳极区，第一基极区，第一基极区上的第二基极区和接触第二基极区并与其间限定P-N结的阴极区的晶闸管。 为了提供门控关断控制，耗尽型场效应晶体管设置在第二基极区上，并通过绝缘区与其分离。 特别地，在第二基极区域上设置绝缘区域，例如埋入介质层，并在其上形成耗尽型场效应晶体管。 耗尽型场效应晶体管电连接在阴极触点和第二基极区之间，并响应于优选为零或接近零偏压的截止偏置信号而在其间提供直接电连接。 另一方面，绝缘区域防止了第二基极区域和耗尽型晶体管的源极之间的直接导电。 绝缘区域可以在加工过程中形成为掩埋介电层，并且优选地选自SiO 2，Si 3 N 4，Al 2 O 3和MgAl 2 O 4。

公开(公告)号：US5111253A

公开(公告)日：1992-05-05

申请号：US576125

申请日：1990-08-28

申请人： Charles S. Korman ,  Bantval J. Baliga ,  Hsueh-Rong Chang

发明人： Charles S. Korman ,  Bantval J. Baliga ,  Hsueh-Rong Chang

IPC分类号： H01L27/07 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L27/0727 ,  H01L29/7806 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/41766

摘要： A semiconductor power switching device comprises a multicellular FET structure with a Schottky barrier diode structure interspersed therewith with at least some of the FET cells being free of Schottky barrier portions. The ratio of Schottky barrier contact area to FET cell area in the overall device may be adjusted to tailor the device for operation at specific current densities.

摘要翻译： 半导体功率开关器件包括具有散布于其中的肖特基势垒二极管结构的多细胞FET结构，其中至少一些FET单元没有肖特基势垒部分。 可以调节整个装置中的肖特基势垒接触面积与FET单元面积的比例，以调整装置以在特定电流密度下操作。