公开(公告)号：US20190165287A1

公开(公告)日：2019-05-30

申请号：US16033143

申请日：2018-07-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hongwei Tian ,  Yanan Niu ,  Meng Zhao ,  Zheng Liu

IPC: H01L51/00 ,  H01L51/52 ,  H01L51/56 ,  H01L27/32 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08

Abstract: A flexible display substrate, a method for manufacturing the same, a flexible display panel, and a flexible display device. The flexible display substrate includes: a flexible base substrate including a bendable region and an unbendable region, the bendable region including a bendable edge and an unbendable edge, the unbendable edge extending in a first direction; and at least one transistor in the bendable region of the flexible base substrate, including a gate electrode, a source region, a drain region, and an active layer, wherein the active layer extends in a direction substantially parallel to the first direction.

公开(公告)号：US10276100B2

公开(公告)日：2019-04-30

申请号：US15531561

申请日：2016-11-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Zhanjie Ma ,  Lintao Zhang ,  Tuo Sun ,  Zheng Liu

IPC: G09G3/3233 ,  G09G3/3258

Abstract: A pixel circuit and driving method, an array substrate, a display panel, and a display device are provided. The pixel circuit includes a voltage clamping unit, an energy storage unit, and a reference voltage terminal. The voltage clamping unit connects to the reference voltage terminal and a first terminal of the energy storage unit. The voltage clamping unit forms a voltage divider circuit to supply a divided reference voltage from the reference voltage terminal to the first terminal of the energy storage unit or pulls and clamps the voltage at the first terminal of the energy storage unit to a reference voltage at the reference voltage terminal.

公开(公告)号：US10241361B2

公开(公告)日：2019-03-26

申请号：US15503046

申请日：2016-07-05

Applicant: Boe Technology Group Co., Ltd. ,  Beijing Boe Display Technology Co., Ltd.

Inventor： Zhichao Zhang ,  Tsungchieh Kuo ,  Zheng Liu ,  Mingxuan Liu ,  Shoukun Wang ,  Jingjing Jiang

IPC: G02F1/1335

Abstract: A color film substrate comprises: a basal substrate, a plurality of color filters of at least one color formed on the basal substrate, and a black matrix formed on the basal substrate. The black matrix has a plurality of openings one-to-one corresponding to the plurality of color filters of at least one color. In a cross section perpendicular to the basal substrate, an edge of the color filter and an opening edge of the black matrix have an overlapping region. According to the color film substrate, manufacturing method thereof and display device provided by the embodiments of the present disclosure, by applying the technology of halftone mask plate and positive/negative photoresist, the patterns for the plurality of color filters of the at least one color and the pattern of the black matrix can be formed with one filter mask plate.

公开(公告)号：US10205049B2

公开(公告)日：2019-02-12

申请号：US14436141

申请日：2014-07-29

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

Inventor： Xiaoxiang Zhang ,  Zheng Liu ,  Zongjie Guo

IPC: H01L27/12 ,  H01L27/32 ,  H01L21/768 ,  H01L33/00 ,  H01L33/42 ,  H01L33/44 ,  H01L33/58 ,  G02B27/22 ,  G02B5/00

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed. The masking steps for forming the insulating layer and the transparent electrode layer may be decreased due to the half tone masking process, thus, the manufacturing process is simplified and the manufacturing efficiency is increased, and the cost for manufacturing the light barrier substrate is lowered because the mask is less used in the manufacturing process.

公开(公告)号：US20180374908A1

公开(公告)日：2018-12-27

申请号：US15737191

申请日：2017-06-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong Li ,  Yi Li ,  Xiaowei Xu ,  Zheng Liu

IPC: H01L27/32

CPC classification number: H01L27/326 ,  H01L27/3206 ,  H01L27/3216 ,  H01L27/3218 ,  H01L27/3246 ,  H01L27/3272 ,  H01L51/0011 ,  H01L51/0017 ,  H01L2251/558

Abstract: A display substrate, a method for manufacturing the same, a display panel and a display device are disclosed. The display substrate includes a pixel unit, and the pixel unit includes a light emitting layer and a pixel definition layer surrounding the light emitting layer. The pixel definition layer includes a first region and a second region. The first region has a first thickness, the second region has a second thickness. The first thickness is greater than the second thickness.

公开(公告)号：US09985116B2

公开(公告)日：2018-05-29

申请号：US15350844

申请日：2016-11-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaolong Li ,  Zheng Liu ,  Dong Li ,  Huijuan Zhang ,  Jian Min

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32132 ,  H01L29/78675

Abstract: A method for processing a polysilicon thin film and a method for fabricating a thin film transistor are provided. The method for processing a polysilicon thin film includes: etching the polysilicon thin film using etching particles. An angle between an incident direction of the etching particles and the polysilicon thin film is larger than 0° and less than 90°.

公开(公告)号：US09899225B2

公开(公告)日：2018-02-20

申请号：US15105175

申请日：2015-09-10

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

Inventor： Zhichao Zhang ,  Tsung-Chieh Kuo ,  Zheng Liu ,  Xiaoxiang Zhang ,  Xi Chen ,  Mingxuan Liu

IPC: H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L21/28008 ,  G02F1/1362 ,  G02F1/1368 ,  G02F2001/136236 ,  G02F2001/13685 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66742

Abstract: An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.

公开(公告)号：US09880439B2

公开(公告)日：2018-01-30

申请号：US15309499

申请日：2016-03-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu

IPC: G02F1/1368 ,  H01L27/12 ,  G02F1/1343 ,  H01L21/265 ,  H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/167 ,  H01L29/66

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F2001/13685 ,  H01L21/26513 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

Abstract: A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.

公开(公告)号：US09837542B2

公开(公告)日：2017-12-05

申请号：US15104504

申请日：2015-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xialong Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

公开(公告)号：US20170133512A1

公开(公告)日：2017-05-11

申请号：US15104504

申请日：2015-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xiaolong Li

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: The disclosure provides a polycrystalline silicon thin-film transistor and a method for manufacturing the same as well as a display device. The polycrystalline silicon thin-film transistor comprises: a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same provided by the disclosure, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.