公开(公告)号：US07101763B1

公开(公告)日：2006-09-05

申请号：US10908556

申请日：2005-05-17

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L29/38

CPC分类号： H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

摘要： The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. The method of the present invention includes providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on the bottom Si layer; forming a well region and isolation regions via implantation within the bottom Si layer; forming an undercut region beneath the top Si layer by etching back the SiGe layer; and filling the undercut with a dielectric to provide device isolation, wherein the dielectric has an outer vertical edge that is aligned to an outer vertical edge of the top Si layer.

摘要翻译： 本发明提供了一种用于在体Si衬底上产生FinFET器件的基于SiGe的体积集成方案，其中已经添加了简单的蚀刻，掩模，离子注入组序列以实现良好的结隔离，同时保持FinFET的低电容益处。 本发明的方法包括提供包括底部Si层和在底部Si层上包含SiGe层和顶部Si层的图案化叠层的结构; 通过在底部Si层内的注入形成阱区和隔离区; 通过蚀刻SiGe层在顶部Si层下方形成底切区域; 并用电介质填充底切以提供器件隔离，其中电介质具有与顶部Si层的外部垂直边缘对准的外部垂直边缘。

公开(公告)号：US07087966B1

公开(公告)日：2006-08-08

申请号：US10908583

申请日：2005-05-18

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L31/0392

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。

公开(公告)号：US07009265B2

公开(公告)日：2006-03-07

申请号：US10710007

申请日：2004-06-11

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7835 ,  H01L29/785

摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.

摘要翻译： 场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。 底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。 下层区域减少重叠电容，从而提高开关速度。 欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。 因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

公开(公告)号：US06998684B2

公开(公告)日：2006-02-14

申请号：US10708907

申请日：2004-03-31

申请人： Brent A. Anderson ,  MeiKei Leong ,  Edward J. Nowak

发明人： Brent A. Anderson ,  MeiKei Leong ,  Edward J. Nowak

IPC分类号： H01L27/01

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/982

摘要： Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

摘要翻译： 公开了具有至少两种晶体取向的基板的集成电路结构。 第一类型晶体管（例如，NFET）形成在具有第一类型晶体取向的衬底的第一部分上，并且第二类型晶体管（例如，PFET）形成在具有第二类型晶体取向的衬底的第二部分上 。 衬底的一些第一部分包括非浮动衬底部分，并且衬底中的剩余部分和第二部分中的其余部分包括浮动衬底部分。

公开(公告)号：US06962843B2

公开(公告)日：2005-11-08

申请号：US10605905

申请日：2003-11-05

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming a protective layer on at least one sidewall of the fin; and (e) removing the protective layer from the at least one sidewall in a channel region of the fin. In a second embodiment, the protective layer is converted to a protective spacer.

摘要翻译： FinFET结构和形成FinFET器件的方法。 该方法包括：（a）提供半导体衬底，（b）在衬底的顶表面上形成电介质层; （c）在所述电介质层的顶表面上形成硅鳍片; （d）在翅片的至少一个侧壁上形成保护层; 和（e）在所述翅片的通道区域中从所述至少一个侧壁去除所述保护层。 在第二实施例中，保护层被转换成保护间隔物。

公开(公告)号：US06949768B1

公开(公告)日：2005-09-27

申请号：US10711974

申请日：2004-10-18

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.

摘要翻译： 与鳍状场效应晶体管（FinFET）集成的平面基板器件和制造方法包括：包括衬底的绝缘体上硅（SOI）晶片; 衬底上的掩埋绝缘体层; 以及掩埋绝缘体层上的半导体层。 所述结构还包括在所述掩埋绝缘体层上的FinFET和集成在所述衬底中的场效应晶体管（FET），其中所述FET栅极与所述FinFET栅极平面。 该结构还包括在衬底中配置的逆行阱区。 在一个实施例中，该结构还包括在衬底中配置的浅沟槽隔离区域。

公开(公告)号：US09231085B2

公开(公告)日：2016-01-05

申请号：US13403457

申请日：2012-02-23

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

摘要： FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel on a silicon layer of a substrate comprising an underlying insulator layer. The method further includes etching the silicon layer to form at least one silicon island under the at least one mandrel. The method further includes ion-implanting sidewalls of the at least one silicon island to form doped regions on the sidewalls. The method further includes forming a dielectric layer on the substrate, a top surface of which is planarized to be coplanar with a top surface of the at least one mandrel. The method further includes removing the at least one mandrel to form an opening in the dielectric layer. The method further includes etching the at least one silicon island to form at least one fin island having doped source and drain regions.

摘要翻译： FinFET端部注入半导体结构和制造方法在本文中公开。 该方法包括在包括下面的绝缘体层的衬底的硅层上形成至少一个心轴。 该方法还包括蚀刻硅层以在至少一个心轴下形成至少一个硅岛。 该方法还包括离子注入至少一个硅岛的侧壁以在侧壁上形成掺杂区域。 所述方法还包括在所述基底上形成电介质层，所述电介质层的顶表面被平坦化以与所述至少一个心轴的顶表面共面。 该方法还包括去除至少一个心轴以在电介质层中形成开口。 该方法还包括蚀刻至少一个硅岛以形成具有掺杂源极和漏极区域的至少一个鳍岛。

公开(公告)号：US09059319B2

公开(公告)日：2015-06-16

申请号：US12692760

申请日：2010-01-25

申请人： Brent A. Anderson ,  John E. Barth, Jr. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

发明人： Brent A. Anderson ,  John E. Barth, Jr. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

IPC分类号： H01L27/108 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L21/84 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.

摘要翻译： 本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法 晶圆。 本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

公开(公告)号：US08946049B2

公开(公告)日：2015-02-03

申请号：US13444447

申请日：2012-04-11

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L27/088 ,  H01L21/762

CPC分类号： H01L27/088 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

摘要： Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement gate structures.

摘要翻译： 公开了门结构和制造方法。 该方法包括在介电材料形成的沟槽内形成连续的置换栅结构。 该方法还包括将连续替换栅极结构分割成单独的替换栅极结构。 该方法还包括在单独的替换栅极结构之间形成绝缘体材料。

公开(公告)号：US08946027B2

公开(公告)日：2015-02-03

申请号：US13367725

申请日：2012-02-07

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

摘要翻译： 鳍状场效应晶体管（FinFET）结构和制造FinFET的方法，其包括形成在沟道区的每个端部上的沟道区和源/漏（S / D）区的硅鳍，其中整个底表面 沟道区域接触下绝缘体的顶表面，S / D区的底表面接触下硅锗（SiGe）层的顶表面的第一部分。 FinFET结构还包括接触顶部表面的外部S / D区域和下部SiGe层的顶表面的每个S / D区域和第二部分的两个侧表面。 FinFET结构还包括形成在通道区域的顶表面和两个侧表面上的适形电介质的替代栅极或栅极堆叠。