公开(公告)号：US20070269945A1

公开(公告)日：2007-11-22

申请号：US11830489

申请日：2007-07-30

申请人： Meikei Ieong ,  Min Yang

发明人： Meikei Ieong ,  Min Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  Y10S438/973

摘要： The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

摘要翻译： 本发明提供了一种集成半导体器件的方法，使得在混合基板的特定晶体取向上形成不同类型的器件，其增强了每种器件的性能。 具体地，本发明提供了一种集成半导体器件的方法，使得pFET位于（110）晶面上，而nFET位于平面混合衬底的（100）晶面上。 本发明的方法还通过埋层绝缘体和反掺杂层的组合来改进制造SOI类器件的性能。 本发明还涉及利用本发明的方法形成的半导体结构。

公开(公告)号：US07087965B2

公开(公告)日：2006-08-08

申请号：US10830347

申请日：2004-04-22

申请人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

公开(公告)号：US07023055B2

公开(公告)日：2006-04-04

申请号：US10696634

申请日：2003-10-29

申请人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

发明人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/76254 ,  H01L21/823807

摘要： A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

公开(公告)号：US06946696B2

公开(公告)日：2005-09-20

申请号：US10328285

申请日：2002-12-23

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01C27/148

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US20050145837A1

公开(公告)日：2005-07-07

申请号：US10980220

申请日：2004-11-03

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

公开(公告)号：US20050070077A1

公开(公告)日：2005-03-31

申请号：US10967398

申请日：2004-10-18

申请人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

发明人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08 ,  H01L29/04

CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

公开(公告)号：US06815278B1

公开(公告)日：2004-11-09

申请号：US10647395

申请日：2003-08-25

申请人： Meikei Ieong ,  Min Yang

发明人： Meikei Ieong ,  Min Yang

IPC分类号： H01L218234

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/78654 ,  H01L29/78684

摘要： The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer. A semiconductor material is epitaxial grown in the opening and then various etching and etch back processing steps are used in forming the SOI substrate.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供了最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 通过将开口形成为至少包括具有不同晶体取向的第一半导体层和第二半导体层的结构，形成SOI衬底。 开口延伸到第一半导体层。 半导体材料在开口中外延生长，然后在形成SOI衬底中使用各种蚀刻和回蚀加工步骤。

公开(公告)号：US07605429B2

公开(公告)日：2009-10-20

申请号：US11107611

申请日：2005-04-15

申请人： Kerry Bernstein ,  Jeffrey W. Sleight ,  Min Yang

发明人： Kerry Bernstein ,  Jeffrey W. Sleight ,  Min Yang

IPC分类号： H01L29/72

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

摘要翻译： 本发明提供了一种半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化从SOI和体硅区域FET的组合构建的电路的功率和性能。

公开(公告)号：US07250658B2

公开(公告)日：2007-07-31

申请号：US11122193

申请日：2005-05-04

申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

IPC分类号： H01L29/772

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

公开(公告)号：US06667528B2

公开(公告)日：2003-12-23

申请号：US10033902

申请日：2002-01-03

申请人： Guy Moshe Cohen ,  Kern Rim ,  Dennis L. Rogers ,  Jeremy Daniel Schaub ,  Min Yang

发明人： Guy Moshe Cohen ,  Kern Rim ,  Dennis L. Rogers ,  Jeremy Daniel Schaub ,  Min Yang

IPC分类号： H01L31058

CPC分类号： H01L31/105 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.

摘要翻译： 光电检测器（及其制造方法）包括半导体衬底，形成在衬底上的埋入绝缘体，形成在埋层绝缘体上的掩埋反射镜，形成在导体上的绝缘体上半导体层（SOI）层， 形成在绝缘体上半导体层中的p型和p型掺杂指，以及与p型掺杂指和n型掺杂指之一的背面接触。