公开(公告)号：US07256439B2

公开(公告)日：2007-08-14

申请号：US10905808

申请日：2005-01-21

申请人： Kangguo Cheng ,  Babar A. Khan ,  Carl J. Radens

发明人： Kangguo Cheng ,  Babar A. Khan ,  Carl J. Radens

IPC分类号： H01L31/119

CPC分类号： H01L29/945

摘要： According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.

摘要翻译： 根据本发明的一个方面，提供了一种结构，其中沟槽电容器阵列包括与合并的掩埋板扩散区的阱接触。 布置在基板中的阵列包括用于接收参考电位的触点。 每个沟槽电容器包括形成在沟槽内的节点电介质和节点导体。 掩埋板（BP）扩散从阵列的每个沟槽的下部横向向外延伸，BP扩散合并以在阵列上形成至少基本上连续的BP扩散区域。 隔离区域在BP扩散区域的一部分上延伸。 在衬底内形成掺杂阱区，该衬底从衬底的主表面延伸至低于基本上连续的BP扩散区的顶层的深度。 还向阱区域提供电互连。

公开(公告)号：US07214910B2

公开(公告)日：2007-05-08

申请号：US10884933

申请日：2004-07-06

申请人： Howard Hao Chen ,  William J. Ferrante ,  Louis L. Hsu ,  Carl J. Radens

发明人： Howard Hao Chen ,  William J. Ferrante ,  Louis L. Hsu ,  Carl J. Radens

IPC分类号： H05B1/02

CPC分类号： G05D23/20 ,  G05D23/1931 ,  Y10T307/469

摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

摘要翻译： 片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。 如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

公开(公告)号：US07138685B2

公开(公告)日：2006-11-21

申请号：US10318495

申请日：2002-12-11

申请人： Louis L. Hsu ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Louis L. Hsu ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L21/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为平坦绝缘体上形成平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。

公开(公告)号：US07132324B2

公开(公告)日：2006-11-07

申请号：US10905002

申请日：2004-12-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

公开(公告)号：US07105445B2

公开(公告)日：2006-09-12

申请号：US11034890

申请日：2005-01-14

申请人： Kwong-Hon Wong ,  Louis C. Hsu ,  Timothy J. Dalton ,  Carl J. Radens ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Theodorus E. Standaert

发明人： Kwong-Hon Wong ,  Louis C. Hsu ,  Timothy J. Dalton ,  Carl J. Radens ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Theodorus E. Standaert

IPC分类号： H01L21/44

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连的方法，其包括在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸，并且在所述互连结构的所述延伸部分上沉积包封盖 。

公开(公告)号：US07084449B2

公开(公告)日：2006-08-01

申请号：US10710146

申请日：2004-06-22

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  David R. Hanson ,  Carl J. Radens

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  David R. Hanson ,  Carl J. Radens

IPC分类号： H01L27/108 ,  H01L29/00

CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/945

摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.

摘要翻译： 提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。 微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处， 并且第二电容器的顶部设置在距离主表面的第二深度处。

公开(公告)号：US07041525B2

公开(公告)日：2006-05-09

申请号：US10751205

申请日：2004-01-02

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L21/66 ,  H01L21/00

CPC分类号： H01L27/14634 ,  H01L27/1463 ,  H01L27/14643

摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

公开(公告)号：US07009237B2

公开(公告)日：2006-03-07

申请号：US10709450

申请日：2004-05-06

申请人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/108

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

公开(公告)号：US06943409B1

公开(公告)日：2005-09-13

申请号：US10709699

申请日：2004-05-24

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/76

CPC分类号： B82Y20/00 ,  H01L27/1446 ,  H01L31/03529 ,  H01L31/105 ,  H01L31/1804 ,  Y02E10/547

摘要： A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the device to fill the wide trench partially and to fill the narrow trench completely. Etch back the first fill material until completion of removal thereof from the wide trench. Form a second electrode in the wide trench by filling the wide trench with a second fill material of an opposite conductivity type. Anneal to drive dopant both from the first fill material of the first electrode into a first outdiffusion region in the substrate about the periphery of the narrow trench and from the second fill material of the second electrode into a second outdiffusion region in the substrate about the periphery of the wide trench.

摘要翻译： 半导体器件形成在半导体衬底上，从第一步骤开始，其在衬底中形成宽沟槽和窄沟槽。 然后通过在器件上沉积第一导电类型的第一填充材料，以便部分填充宽沟槽并完全填充窄沟槽，在窄沟槽中形成第一电极。 将第一填充材料回扫，直到完成从宽沟槽中移除。 通过用相反导电类型的第二填充材料填充宽沟槽在宽沟槽中形成第二电极。 退火以将掺杂剂从第一电极的第一填充材料驱动到衬底周围的窄沟槽的第一外扩散区域中，并且从第二电极的第二填充材料移动到衬底周围的第二外扩散区域 的宽沟。

公开(公告)号：US06759702B2

公开(公告)日：2004-07-06

申请号：US10261559

申请日：2002-09-30

申请人： Carl J. Radens ,  Ramachandra Divakaruni ,  Jack A. Mandelman

发明人： Carl J. Radens ,  Ramachandra Divakaruni ,  Jack A. Mandelman

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.

摘要翻译： 一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器 深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物 与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线 以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触 国际地区。 深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小 比一个光刻特征尺寸。 优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。 该结构对于亚8F 2细胞特别有用。