公开(公告)号：US07443638B2

公开(公告)日：2008-10-28

申请号：US10907974

申请日：2005-04-22

申请人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

发明人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

IPC分类号： G11B5/39 ,  G11B5/33

CPC分类号： G11B5/3929 ,  B82Y10/00 ,  G11B2005/3996

摘要： Disclosed herein is a magnetoresistive structure, for example useful as a spin-valve or GMR stack in a magnetic sensor, and a fabrication method thereof. The magnetoresistive structure uses twisted coupling to induce a perpendicular magnetization alignment between the free layer and the pinned layer. Ferromagnetic layers of the free and pinned layers are exchange-coupled using antiferromagnetic layers having substantially parallel exchange-biasing directions. Thus, embodiments can be realized that have antiferromagnetic layers formed of a same material and/or having a same blocking temperature. At least one of the free and pinned layers further includes a second ferromagnetic layer and an insulating layer, such as a NOL, between the two ferromagnetic layers. The insulating layer causes twisted coupling between the two ferromagnetic layers, rotating the magnetization direction of one 90 degrees relative to the magnetization direction of the other.

摘要翻译： 这里公开了一种例如在磁传感器中用作自旋阀或GMR堆叠的磁阻结构及其制造方法。 磁阻结构使用扭转耦合来引起自由层和被钉扎层之间的垂直磁化对准。 使用具有基本平行的交换偏压方向的反铁磁层来交换耦合自由和被钉扎层的铁磁层。 因此，可以实现具有由相同材料形成的反铁磁层和/或具有相同阻挡温度的实施例。 自由和被钉扎层中的至少一个还包括在两个铁磁层之间的第二铁磁层和绝缘层，例如NOL。 绝缘层引起两个铁磁层之间的扭转耦合，使相对于另一个的磁化方向旋转90度的磁化方向。

公开(公告)号：US07265038B2

公开(公告)日：2007-09-04

申请号：US10723509

申请日：2003-11-25

申请人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

发明人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

IPC分类号： H01L21/26

CPC分类号： H01L21/76807 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

摘要翻译： 铜填充镶嵌结构及其形成方法，包括提供包括半导体衬底的衬底; 在所述基板上形成绝缘体层; 通过所述绝缘体层的厚度部分形成镶嵌开口; 形成扩散阻挡层以使所述镶嵌开口成线; 形成覆盖所述扩散阻挡层的第一晶种层; 用包含选自氩，氮，氢和NH 3的等离子体源气体的第一处理等离子体原位处理第一籽晶层; 形成覆盖所述第一种子层的第二种子层; 根据电化学电镀（ECP）工艺形成覆盖在第二晶种层上的铜层以填充镶嵌开口; 并且平坦化铜层以形成金属互连结构。

公开(公告)号：US20070099402A1

公开(公告)日：2007-05-03

申请号：US11613462

申请日：2006-12-20

申请人： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

发明人： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L23/544 ,  H01L21/67115 ,  H01L29/045 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.

摘要翻译： 可靠的半导体结构及其制造方法。 半导体衬底上的有源区和/或划线沿着耐裂纹结晶方向配置。 可以避免由于快速热处理的突然温度斜坡导致的热裂纹。

公开(公告)号：US07205632B2

公开(公告)日：2007-04-17

申请号：US10818009

申请日：2004-04-05

申请人： Wen-Chin Lin ,  Denny D. Tang ,  Chao-Hsiung Wang

发明人： Wen-Chin Lin ,  Denny D. Tang ,  Chao-Hsiung Wang

IPC分类号： H01L29/00

CPC分类号： H01L21/263 ,  H01L27/0688 ,  H01L27/08

摘要： A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.

摘要翻译： 一种微电子器件，包括至少部分地位于衬底上的半导体器件，至少部分地位于衬底上并且邻近半导体器件的轰击区域，以及插入半导体器件和被轰击区域的轰击衰减器。

公开(公告)号：US20070075428A1

公开(公告)日：2007-04-05

申请号：US11241355

申请日：2005-09-30

申请人： Chao-Hsiung Wang ,  Ping-Kun Wu

发明人： Chao-Hsiung Wang ,  Ping-Kun Wu

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.

摘要翻译： 一种集成电路装置，包括部分嵌入和封装的镶嵌结构及其形成方法以改善与上覆介质层的粘合性，所述集成电路器件包括部分地嵌入形成在介电层中的开口中的导电材料; 其中所述导电材料被封装有包括侧壁和底部的第一阻挡层和覆盖顶部的第二阻挡层，所述导电材料和第一阻挡层侧壁部分延伸到介电层的上表面上方的预定高度以形成 部分嵌入的镶嵌。

公开(公告)号：US07151271B2

公开(公告)日：2006-12-19

申请号：US10681541

申请日：2003-10-08

申请人： Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai

发明人： Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai

IPC分类号： A61N5/00 ,  G21G5/00

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00

摘要： A method and system is disclosed for concentrating high energy particles on a predetermined area on a target semiconductor substrate. A high energy source for generating a predetermined amount of high energy particles, and an electro-magnetic radiation source for generating low energy beams are used together. The system also uses a mask set having at least one mask with at least one alignment area and at least one mask target area thereon, the mask target area passing more high energy particles then any other area of the mask. At least one protection shield is incorporated in the system for protecting the alignment area from being exposed to the high energy particles, wherein the mask is aligned with the predetermined target semiconductor substrate by passing the low energy beams through the alignment area, wherein the high energy particles generated by the high energy source pass through the mask target area to land on the predetermined area on the target semiconductor substrate.

摘要翻译： 公开了一种用于将高能粒子集中在目标半导体衬底上的预定区域上的方法和系统。 用于产生预定量的高能粒子的高能量源和用于产生低能量束的电磁辐射源一起使用。 该系统还使用具有至少一个具有至少一个对准区域和至少一个掩模目标区域的掩模的掩模组，掩模目标区域通过更多的高能粒子，然后通过掩模的任何其它区域。 至少一个保护屏蔽被并入系统中，用于保护对准区域不暴露于高能粒子，其中通过使低能量束通过对准区域，掩模与预定目标半导体衬底对齐，其中高能量 由高能量源产生的粒子通过掩模对象区域落在目标半导体衬底上的预定区域上。

公开(公告)号：US07071007B2

公开(公告)日：2006-07-04

申请号：US10313776

申请日：2002-12-06

申请人： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

发明人： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

IPC分类号： H01L21/00

CPC分类号： H01L28/55

摘要： A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.

摘要翻译： 形成低电压驱动薄膜铁电电容器的方法包括以下步骤：在底部电极上沉​​积铁电和铂薄膜电介质层，对电介质层进行退火，其中形成纳米复合材料层，包括铂纳米颗粒并形成顶部 电极在电介质层上。 还提供了包括铁电电容器的集成电路。 电容器包括形成在衬底上的底部电极和形成在底部电极上的铁电和铂薄膜纳米复合电介质层，其中纳米复合层包括铂纳米颗粒。 在电介质层上形成顶部电极。

公开(公告)号：US20060097316A1

公开(公告)日：2006-05-11

申请号：US10977236

申请日：2004-10-28

申请人： Hao-Yu Chen ,  Fu-Liang Yang ,  Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang

发明人： Hao-Yu Chen ,  Fu-Liang Yang ,  Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

公开(公告)号：US20060038214A1

公开(公告)日：2006-02-23

申请号：US11253178

申请日：2005-10-18

申请人： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

发明人： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

IPC分类号： H01L29/00

CPC分类号： H01L28/55

摘要： A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.

摘要翻译： 形成低电压驱动薄膜铁电电容器的方法包括以下步骤：在底部电极上沉​​积铁电和铂薄膜电介质层，对电介质层进行退火，其中形成纳米复合材料层，包括铂纳米颗粒并形成顶部 电极在电介质层上。 还提供了包括铁电电容器的集成电路。 电容器包括形成在衬底上的底部电极和形成在底部电极上的铁电和铂薄膜纳米复合电介质层，其中纳米复合层包括铂纳米颗粒。 在电介质层上形成顶部电极。

公开(公告)号：US20050236616A1

公开(公告)日：2005-10-27

申请号：US10831981

申请日：2004-04-26

申请人： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

发明人： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L23/544 ,  H01L29/02 ,  H01L29/04

CPC分类号： H01L23/544 ,  H01L21/67115 ,  H01L29/045 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.

摘要翻译： 可靠的半导体结构及其制造方法。 半导体衬底上的有源区和/或划线沿着耐裂纹结晶方向配置。 可以避免由于快速热处理的突然温度斜坡导致的热裂纹。