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    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    63.
    发明授权
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US07238989B2

    公开(公告)日：2007-07-03

    申请号：US11201990

    申请日：2005-08-11

    Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC: H01L27/01

    CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance
    66.
    发明申请
    CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance 审中-公开
    CMOS器件具有选择性形成和回填的半导体衬底区域，以提高器件性能

    公开(公告)号：US20060118878A1

    公开(公告)日：2006-06-08

    申请号：US11003844

    申请日：2004-12-02

    Applicant: Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

    Inventor： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

    IPC: H01L29/94 ,  H01L21/8238

    CPC classification number: H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    Abstract: An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically patterning the semiconductor substrate and etching respective recessed areas including the respective NMOS and PMOS device regions into the silicon semiconductor substrate to a predetermined depth; backfilling the respective recessed areas with at least one semiconductor alloy; and, forming gate structures and offset spacers over the respective NMOS and PMOS device regions.

    Abstract translation: 具有选择的应力水平和施加在相应沟道区上的类型的NMOS和PMOS器件对及其形成方法，所述方法包括提供半导体衬底; 形成隔离区以分离包括PMOS器件区和NMOS器件区的有源区; 将半导体衬底光刻图形化并将包括各个NMOS和PMOS器件区域的各个凹陷区域蚀刻到硅半导体衬底中至预定深度; 用至少一种半导体合金回填相应的凹陷区域; 以及在各个NMOS和PMOS器件区域上形成栅极结构和偏置间隔物。

    Transistor with a strained region and method of manufacture
    67.
    发明申请
    Transistor with a strained region and method of manufacture 有权
    具有应变区域的晶体管及其制造方法

    公开(公告)号：US20060081875A1

    公开(公告)日：2006-04-20

    申请号：US10967917

    申请日：2004-10-18

    Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    IPC: H01L31/109 ,  H01L31/0328 ,  H01L29/76

    CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

    Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

    Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    68.
    发明申请
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US20050272188A1

    公开(公告)日：2005-12-08

    申请号：US11201990

    申请日：2005-08-11

    Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    MRAM DEVICE HAVING LOW-K INTER-METAL DIELECTRIC
    69.
    发明申请
    MRAM DEVICE HAVING LOW-K INTER-METAL DIELECTRIC 有权
    具有低K金属间电介质的MRAM器件

    公开(公告)号：US20050224850A1

    公开(公告)日：2005-10-13

    申请号：US10816730

    申请日：2004-04-02

    Applicant: Chun-Chieh Lin

    Inventor： Chun-Chieh Lin

    IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L29/76 ,  H01L31/119 ,  H01L43/00

    CPC classification number: H01L27/228 ,  B82Y10/00

    Abstract: A magnetic random access memory (MRAM) device including a magnetic tunneling junction (MTJ) stack separated from one or more proximate conductive layers and/or one or more proximate MTJ stacks by a low-k dielectric material.

    Abstract translation: 磁性随机存取存储器（MRAM）装置包括通过低k电介质材料从一个或多个邻近导电层和/或一个或多个邻近MTJ堆叠分离的磁隧道结（MTJ）堆叠。

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