公开(公告)号：US20080165589A1

公开(公告)日：2008-07-10

申请号：US11969856

申请日：2008-01-04

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/22

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 一种用于在包括串行外设接口存储器件的集成电路中读取的双I / O数据的方法。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20080123406A1

公开(公告)日：2008-05-29

申请号：US11555849

申请日：2006-11-02

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.

摘要翻译： 用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。 感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。 第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。 在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

公开(公告)号：US06188590B1

公开(公告)日：2001-02-13

申请号：US08860151

申请日：1997-06-17

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang

IPC分类号： H02M318

CPC分类号： H02M3/073 ,  H02M2003/076

摘要： The present invention discloses a regulator system (112) for regulating the output current and voltage (Vout) of a charge pump circuit (104). It is observed that the output current and voltage (Vout) of a charge pump circuit (104) can be regulated by varying the amplitude and frequency of a set of clock signals (modulated clocks). The present invention comprises means (decoders 1, 2; AM, FM units) for generating a set of control signals (VAD1-VFDn) as the function of the output current and voltage (Vout). The set of control signals (VAD1-VFDn) is coupled to a clock signal generation circuit (130) that generates a set of clock signals (modulated clocks) having a magnitude and a frequency depending on this set of at least one control signal. This set of clock signals (modulated clocks) is then used to drive the charge pump circuit (104). It is found that this regulator circuit (112) consumes less power than prior art regulator circuits.

摘要翻译： 本发明公开了一种用于调节电荷泵电路（104）的输出电流和电压（Vout）的调节器系统（112）。 观察到可以通过改变一组时钟信号（调制时钟）的幅度和频率来调节电荷泵电路（104）的输出电流和电压（Vout）。 本发明包括用于产生作为输出电流和电压（Vout）的函数的一组控制信号（VAD1-VFDn）的装置（解码器1,2，AM，FM单元）。 该组控制信号（VAD1-VFDn）耦合到时钟信号产生电路（130），该时钟信号产生电路产生具有取决于该组至少一个控制信号的幅度和频率的一组时钟信号（调制时钟）。 然后，该组时钟信号（调制时钟）用于驱动电荷泵电路（104）。 发现该调节器电路（112）比现有技术的调节器电路消耗更少的功率。

公开(公告)号：US6002630A

公开(公告)日：1999-12-14

申请号：US29945

申请日：1998-03-04

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： G11C5/14 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/147

摘要： An on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts) includes a sense circuit on the integrated circuit which generates an output indicating a level of the supply voltage. The on chip voltage supply circuit generates the on chip voltage in response to the output of the sense circuit and the supply voltage. The sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage in response. The on chip voltage supply circuit generates the word line voltage at a node coupled to word line driving circuits in the device.

摘要翻译： PCT No.PCT / US97 / 21513 Sec。 371日期：1998年3月4日 102（e）1998年3月4日PCT PCT 1997年11月21日PCT公布。 公开号WO99 /​​ 27537 日期1999年6月3日适用于诸如具有低电源电压（例如2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路包括集成电路上的感测电路，其产生指示 电源电压。 片上电压供应电路响应于感测电路的输出和电源电压而产生片上电压。 感测电路输出表示电源电压的电平，使得片上电压供应电路能够适应用于产生片上电压的升压量。 片上电压供应电路在耦合到器件中的字线驱动电路的节点处产生字线电压。

公开(公告)号：US08898439B2

公开(公告)日：2014-11-25

申请号：US12837823

申请日：2010-07-16

申请人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

发明人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

IPC分类号： G06F9/34 ,  G11C7/10 ,  G06F9/30 ,  G06F9/38

CPC分类号： G11C7/10 ,  G06F9/30149 ,  G06F9/342 ,  G06F9/3875

摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

摘要翻译： 串行闪存及其地址发送方法。 串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。 如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。 在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。 第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。

公开(公告)号：US08482987B2

公开(公告)日：2013-07-09

申请号：US12875003

申请日：2010-09-02

申请人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/345 ,  G11C16/3454

摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

公开(公告)号：US08400190B2

公开(公告)日：2013-03-19

申请号：US12565624

申请日：2009-09-23

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Hsieh-Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Hsieh-Ming Chih

IPC分类号： H03K3/00

CPC分类号： H03K3/00 ,  H03K19/0002 ,  H03K19/09425

摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

公开(公告)号：US08347185B2

公开(公告)日：2013-01-01

申请号：US13456870

申请日：2012-04-26

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： G11C29/00 ,  G06F7/02 ,  H03M13/00

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。

公开(公告)号：US08341330B2

公开(公告)日：2012-12-25

申请号：US11970468

申请日：2008-01-07

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

摘要： A method for reading data in an integrated circuit includes receiving a read command, which is associated with an enhanced data read, and receiving a first address from a plurality of input/output pins. The method includes receiving a first performance enhancement indicator and determining whether an enhanced read operation is to be performed based on at least information associated with the first performance enhancement indicator. The method includes waiting n clock cycles, where n is an integer, then outputting data from a memory array in the integrated circuit using the plurality of input/output pins concurrently. The method also includes performing an enhanced read operation, if it is determined that the enhanced read operation is to be performed. In an embodiment of the method, performing an enhanced read operation includes receiving a second address and a second performance enhance indicator without receiving a read command.

摘要翻译： 一种用于在集成电路中读取数据的方法包括接收与增强数据读取相关联的读取命令，以及从多个输入/输出引脚接收第一地址。 所述方法包括接收第一性能增强指示符并且基于至少基于与所述第一性能增强指示符相关联的信息来确定是否要执行增强的读取操作。 该方法包括等待n个时钟周期，其中n是整数，然后同时使用多个输入/输出引脚从集成电路中的存储器阵列输出数据。 如果确定要执行增强的读取操作，则该方法还包括执行增强的读取操作。 在该方法的实施例中，执行增强的读取操作包括接收第二地址和第二性能增强指示符而不接收读取命令。

公开(公告)号：US20120300562A1

公开(公告)日：2012-11-29

申请号：US13564189

申请日：2012-08-01

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C7/00

CPC分类号： G11C29/10 ,  G11C29/12005

摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

摘要翻译： 提供了一种用于测试多芯片封装的方法和电路。 多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。 该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。