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公开(公告)号：US10171049B2
公开(公告)日：2019-01-01
申请号：US15726584
申请日：2017-10-06
Inventor： John P. Lesso , Toru Ido
Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.
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公开(公告)号：US20180323705A1
公开(公告)日：2018-11-08
申请号：US16023114
申请日：2018-06-29
Inventor： John P. Lesso , Peter J. Frith , John L. Pennock
CPC classification number: H02M3/07 , H02M1/00 , H02M2001/0083 , H02M2001/009 , H03F3/181
Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.
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公开(公告)号：US09787261B2
公开(公告)日：2017-10-10
申请号：US15278862
申请日：2016-09-28
Inventor： John P. Lesso , Toru Ido
CPC classification number: H03F3/2171 , H03F1/0211 , H03F3/187 , H03F3/217 , H03F2200/165 , H03F2200/171 , H03F2200/333 , H03F2200/351 , H03G1/0088
Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability while reducing switching power losses.
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公开(公告)号：US09685855B2
公开(公告)日：2017-06-20
申请号：US15085360
申请日：2016-03-30
Inventor： John P. Lesso , John L. Pennock , Peter J. Frith
CPC classification number: H02M3/07 , H03F1/025 , H03F3/185 , H03F3/187 , H03F3/68 , H03F2200/507 , H03F2200/511 , H03G1/0017 , H03G1/0029 , H03G1/0088 , H03G1/0094
Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.
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公开(公告)号：US20160336850A1
公开(公告)日：2016-11-17
申请号：US15222095
申请日：2016-07-28
Inventor： John P. Lesso , John L. Pennock , Peter J. Frith
IPC: H02M3/07
CPC classification number: H02M3/07 , H03F1/025 , H03F3/185 , H03F3/187 , H03F3/68 , H03F2200/507 , H03F2200/511 , H03G1/0017 , H03G1/0029 , H03G1/0088 , H03G1/0094
Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.
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Patent Agency Ranking
公开(公告)号：US12149256B2
公开(公告)日：2024-11-19
申请号：US17869344
申请日：2022-07-20
Inventor： John P. Lesso
IPC: H03M1/06
Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT) The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.
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公开(公告)号：US12035631B2
公开(公告)日：2024-07-09
申请号：US16905171
申请日：2020-06-18
Inventor： John P. Lesso
CPC classification number: H10N30/802 , H02N2/062
Abstract: The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: output stage circuitry configured to receive an input signal and to drive the piezoelectric transducer to produce the output signal; variable voltage power supply circuitry configured to output a supply voltage for the charge drive output stage circuitry, wherein the supply voltage output by the variable voltage power supply circuitry varies based on the input signal; a supply capacitor for receiving the supply voltage output by the variable voltage power supply circuitry; a reservoir capacitor; and circuitry for transferring charge between the reservoir capacitor and the supply capacitor.
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公开(公告)号：US11937509B2
公开(公告)日：2024-03-19
申请号：US16951032
申请日：2020-11-18
Inventor： John P. Lesso , Anthony S. Doy
CPC classification number: H10N30/802 , B06B1/0253 , B06B2201/55
Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry comprises pre-processor circuitry configured to process an input signal to generate a processed signal; driver circuitry coupled to the pre-processor circuitry and configured to generate a drive signal, based on the processed signal, for driving the piezoelectric transducer; and processor circuitry configured to determine a resonant frequency of the piezoelectric transducer. The pre-processor circuitry is configured to process the input signal based on the determined resonant frequency so as to generate the processed signal.
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公开(公告)号：US11918345B2
公开(公告)日：2024-03-05
申请号：US18298573
申请日：2023-04-11
Inventor： John P. Lesso , Yanto Suryono , Toru Ido
CPC classification number: A61B5/0823 , A61B5/0803 , A61B5/6803 , A61B5/7246 , A61B5/725 , A61B5/7264 , A61B5/7275 , A61B2562/0219
Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.
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公开(公告)号：US11849643B2
公开(公告)日：2023-12-19
申请号：US17216767
申请日：2021-03-30
Inventor： John P. Lesso , Robert A. Steven
CPC classification number: H10N30/40 , H10N30/20 , H10N30/802
Abstract: Circuitry for estimating a displacement of a piezoelectric transducer in response to a drive signal applied to the piezoelectric transducer, the circuitry comprising: monitoring circuitry configured to be coupled to the piezoelectric transducer and to output a sense signal indicative of an electrical signal associated with the piezoelectric transducer as a result of the drive signal; wherein the circuitry is configured to generate a difference signal based on the drive signal and the sense signal; and wherein the circuitry further comprises processing circuitry configured to apply at least one transfer function to the difference signal to generate a signal indicative of the displacement of the piezoelectric transducer.
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