公开(公告)号：US08743615B2

公开(公告)日：2014-06-03

申请号：US13214765

申请日：2011-08-22

申请人： Dana Lee ,  Ken Oowada

发明人： Dana Lee ,  Ken Oowada

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C11/5642

摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.

摘要翻译： 提供了部分编程的非易失性存储块的读取补偿。 在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。 在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。 如果是这样，那么在阅读请求的页面时可以做出适当的补偿。 该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。 赔偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。 该补偿可以补偿所请求的页面的阈值电压分布的变化，其将从其他页面的后续编程发生。

公开(公告)号：US08614915B2

公开(公告)日：2013-12-24

申请号：US12822584

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

摘要翻译： 公共活动层上的多个非易失性存储元件偏离邻近的非易失性存储元件。 非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。 还描述了制造偏移非易失性存储元件的制造方法。

公开(公告)号：US08406052B2

公开(公告)日：2013-03-26

申请号：US13028847

申请日：2011-02-16

申请人： Dana Lee ,  Hock So

发明人： Dana Lee ,  Hock So

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418 ,  G11C2211/565

摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

摘要翻译： 使用源侧热电子注入编程非易失性存储器。 为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。 在充电之后，将第二低电压施加到与选定位线相邻的未选位线。 由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。 用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

公开(公告)号：US20130070524A1

公开(公告)日：2013-03-21

申请号：US13239194

申请日：2011-09-21

申请人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

发明人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

摘要翻译： 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。

公开(公告)号：USRE43870E1

公开(公告)日：2012-12-25

申请号：US13289108

申请日：2011-11-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

公开(公告)号：US08111552B2

公开(公告)日：2012-02-07

申请号：US12822546

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

摘要翻译： 公共活动层上的多个非易失性存储元件偏离邻近的非易失性存储元件。 非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。 还描述了制造偏移非易失性存储元件的制造方法。

公开(公告)号：US20110134694A1

公开(公告)日：2011-06-09

申请号：US13028847

申请日：2011-02-16

申请人： Dana Lee ,  Hock So

发明人： Dana Lee ,  Hock So

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418 ,  G11C2211/565

摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

摘要翻译： 使用源侧热电子注入编程非易失性存储器。 为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。 在充电之后，将第二低电压施加到与选定位线相邻的未选位线。 由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。 用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

公开(公告)号：US07944749B2

公开(公告)日：2011-05-17

申请号：US11614879

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 一种低电压方法，通过从注入存储器的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到选定位线的漏极节点 小区具有耦合到下一个相邻字线WL（n-1）的门节点到位于字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US07907449B2

公开(公告)日：2011-03-15

申请号：US12421098

申请日：2009-04-09

申请人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

发明人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 使用试验擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。 可以执行第二次擦除之后的软编程。 可以基于试用擦除脉冲来确定软编程脉冲的幅度。 在一个实现中，在软编程之后，不会验证存储单元的阈值电压。 限制擦除脉冲数和软编程脉冲可节省时间和功率。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US20100322015A1

公开(公告)日：2010-12-23

申请号：US12872351

申请日：2010-08-31

申请人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

发明人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。