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公开(公告)号：US20080301337A1
公开(公告)日：2008-12-04
申请号：US12185533
申请日：2008-08-04
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。
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公开(公告)号：US20080140907A1
公开(公告)日：2008-06-12
申请号：US11567549
申请日：2006-12-06
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G06F13/1694
摘要： Multimodal memory controllers are disclosed that include: a transceiver circuit having at least one internal signal line, a first external signal line, a second external signal line, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, and the transceiver circuit configured to operate the external signal lines for single-ended signaling at a first voltage when the mode control signal is a first value and to operate the external signal lines for differential signaling at a second voltage when the mode control signal is a second value.
摘要翻译： 公开了多模式存储器控制器，其包括：具有至少一个内部信号线，第一外部信号线，第二外部信号线和模式控制信号线的收发器电路，模式控制信号线已经在其上断言了模式控制 信号，并且所述收发器电路被配置为当所述模式控制信号是第一值时，以第一电压对所述外部信号线进行单端信令的操作，并且当所述模式控制信号为模式控制信号时，将所述外部信号线用于第二电压的差分信号 是第二个值。
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63.发明申请Signal History Controlled Slew-Rate Transmission Method and Bus Interface Transmitter 失效信号历史控制压摆率传输方法和总线接口发射机公开(公告)号：US20080061826A1
公开(公告)日：2008-03-13
申请号：US11466122
申请日：2006-08-22
IPC分类号： H03K19/0175
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
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公开(公告)号：US07301320B2
公开(公告)日：2007-11-27
申请号：US11040225
申请日：2005-01-21
CPC分类号： H03K5/08 , G01R19/16552 , G01R29/26
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译： 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。 这具有以不需要校准的方式直接感测电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。
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公开(公告)号：US06690196B1
公开(公告)日：2004-02-10
申请号：US10216617
申请日：2002-08-08
IPC分类号： H03K190175
CPC分类号： H04L5/1423
摘要： A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.
摘要翻译： 一种用于在传输线的远端之间发送和接收数据的系统。 该系统具有同步双向（SBIDI）驱动器和接收器，用于在性能良好的传输线路上实现高性能。 SBIDI驱动器和SBIDI接收器由逻辑输入启用和禁用。 单向（UNI）接收器与每个SBIDI接收器并联连接。 逻辑保证SBIDI和UNI接收器不被同时启用。 当需要时，SBIDI接收器被禁用，并且UNI接收器被启用，并且信令是单向的。 可以响应于模式补偿信号修改SBIDI驱动器中的当前电平，以改善单向模式中的信噪比并补偿同时双向模式中的损耗。 该系统可以集成到所有I / O中，以实现最大的设计灵活性。
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66.发明授权Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference 失效具有包括在第一频率工作的振荡器的串行器的接口和包括以第二频率工作的振荡器的解串器等于半第一频率以最小化频率干扰
公开(公告)号：US5490282A
公开(公告)日：1996-02-06
申请号：US988593
申请日：1992-12-08
申请人： Daniel M. Dreps , Raymond P. Rizzo
发明人： Daniel M. Dreps , Raymond P. Rizzo
CPC分类号： H03M9/00
摘要： A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.
摘要翻译： 提供用于发送和接收串行数据的串行通信接口，包括串行器和解串器。 串行器被设计成使得串行器VCO的中心频率是解串器VCO的中心频率的一半。 串行器使用时钟的两边来混合串行位。 解串器设计不变。 两个VCO在独立的芯片上实现，两个芯片位于相同的金属化陶瓷基板上，其间距约为40毫米。 近频互动显着减少。
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公开(公告)号：US09473333B2
公开(公告)日：2016-10-18
申请号：US12028953
申请日：2008-02-11
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译： 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。
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68.发明授权Advanced memory device having improved performance, reduced power and increased reliability 有权先进的存储器件具有改进的性能，降低功率和增加可靠性公开(公告)号：US08659959B2
公开(公告)日：2014-02-25
申请号：US13567353
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。
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69.发明授权公开(公告)号：US08619432B2
公开(公告)日：2013-12-31
申请号：US12895251
申请日：2010-09-30
IPC分类号： H01R9/00
CPC分类号： H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
摘要： Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.
摘要翻译： 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。
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70.发明授权公开(公告)号：US08332552B2
公开(公告)日：2012-12-11
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F3/00 , G06F13/12 , G06F13/00 , G06F13/42 , G06F15/76 , G06F9/44 , H04L12/28 , H04L12/50 , H03K19/173 , H01L25/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
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