公开(公告)号：US20090249302A1

公开(公告)日：2009-10-01

申请号：US12058874

申请日：2008-03-31

申请人： Zheng Xu ,  Suraj Bhaskaran ,  Klas M. Bruce ,  Jason T. Nearing ,  Paul B. Rawlins ,  Matt B. Smittle ,  Michael D. Snyder

发明人： Zheng Xu ,  Suraj Bhaskaran ,  Klas M. Bruce ,  Jason T. Nearing ,  Paul B. Rawlins ,  Matt B. Smittle ,  Michael D. Snyder

IPC分类号： G06F9/44

CPC分类号： G06F11/3636

摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.

摘要翻译： 在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。 基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。 标记位还用于生成按顺序数据跟踪消息。 因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。

公开(公告)号：US20090164737A1

公开(公告)日：2009-06-25

申请号：US11962331

申请日：2007-12-21

申请人： Sanjay R. Deshpande ,  Klas M. Bruce ,  Michael D. Snyder

发明人： Sanjay R. Deshpande ,  Klas M. Bruce ,  Michael D. Snyder

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/507

摘要： A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.

摘要翻译： 处理器为与存储器请求相关联的一致性粒子提供存储器请求和一致性状态值。 处理器还根据一致性状态值是否表示处理器的多个高速缓存的累积一致性状态来进一步提供第一指示符或第二指示符。 第一指示符和第二指示符分别表示相关性状态值，表示累积相关性状态或潜在的非累积一致性状态。 如果提供了第二指示符，则事务管理模块响应于接收到第二指示符来确定是否请求相关性颗粒的累积一致性状态。 响应于确定请求累积一致性状态，事务管理模块向处理器提供对累积一致性状态的请求的指示符。 否则，事务管理模块处理存储器事务而不请求累积一致性状态。

公开(公告)号：US20090113137A1

公开(公告)日：2009-04-30

申请号：US11929180

申请日：2007-10-30

申请人： Brian C. Grayson ,  Klas M. Bruce ,  Anhdung D. Ngo ,  Michael D. Snyder

发明人： Brian C. Grayson ,  Klas M. Bruce ,  Anhdung D. Ngo ,  Michael D. Snyder

IPC分类号： G06F12/08

CPC分类号： G06F12/128 ,  G06F12/122

摘要： A multi-way cache system includes multi-way cache storage circuitry, a pseudo least recently used (PLRU) tree state representative of a PLRU tree, the PLRU tree having a plurality of levels, and PLRU control circuitry coupled to the multi-way cache storage circuitry and the PLRU tree state. The PLRU control circuitry has programmable PLRU tree level update enable circuitry which selects Y levels of the plurality of levels of the PLRU tree to be updated. The PLRU control circuitry, in response to an address hitting or resulting in an allocation in the multi-way cache storage circuitry, updates only the selected Y levels of the PLRU tree state.

摘要翻译： 多路缓存系统包括多路缓存存储电路，代表PLRU树的伪最近最少使用（PLRU）树状态，具有多个电平的PLRU树，以及耦合到多路缓存的PLRU控制电路 存储电路和PLRU树状态。 PLRU控制电路具有可编程PLRU树级更新使能电路，其选择要更新的PLRU树的多个级别的Y级。 PLRU控制电路响应于在多路高速缓存存储电路中的分配地址或导致分配，仅更新PLRU树状态的所选Y级。

公开(公告)号：US20090019170A1

公开(公告)日：2009-01-15

申请号：US11774845

申请日：2007-07-09

申请人： Felix Immanuel Wyss ,  Gregory P. Cunningham ,  Michael D. Snyder ,  Michael L. Szilagyi

发明人： Felix Immanuel Wyss ,  Gregory P. Cunningham ,  Michael D. Snyder ,  Michael L. Szilagyi

IPC分类号： G06F15/16 ,  H04L9/00

CPC分类号： H04L12/66 ,  H04L63/105 ,  H04L65/1069 ,  H04L67/14

摘要： A communication system including a routing server and gateway server through which digital communication sessions are established along selected network routes based upon security requirements is disclosed. A digital communication request having a security level required is transmitted to a routing server. The routing server then determines a route, if available, having a route security rating sufficient for the specified communication and initiates the communication using the gateway server. The route security score is calculated based upon a table of security ratings associated with a plurality of connected networks segments which comprise a digital communication network.

摘要翻译： 公开了一种包括路由服务器和网关服务器的通信系统，通过该路由服务器和网关服务器，基于安全性要求，通过所述路由服务器和网关服务器沿 具有所需安全级别的数字通信请求被发送到路由服务器。 然后，路由服务器确定路由（如果可用）具有对于指定通信足够的路由安全评级，并且使用网关服务器发起通信。 基于与包括数字通信网络的多个连接的网络段相关联的安全评级表来计算路线安全分数。

公开(公告)号：US20080222382A1

公开(公告)日：2008-09-11

申请号：US11682058

申请日：2007-03-05

申请人： Michael D. Snyder

发明人： Michael D. Snyder

IPC分类号： G06F9/26

CPC分类号： G06F11/3471 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/88

摘要： A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.

摘要翻译： 公开了一种性能监视装置和方法。 该设备监视处理器的性能事件。 响应于特定演出事件的发生而调整计数器。 计数器可以与特定指令地址范围或数据地址范围相关联，使得仅当在指令地址范围或数据地址范围发生性能事件时才调整计数器。 因此，可以分析存储在计数器中的信息，以确定特定指令地址范围或数据地址范围是否导致特定的性能事件。 可以使用多个计数器，每个计数器与不同的性能事件，指令地址范围或数据地址范围相关联，以便对程序的哪些部分导致特定的性能事件进行详细分析。

公开(公告)号：US20080183943A1

公开(公告)日：2008-07-31

申请号：US11669804

申请日：2007-01-31

申请人： Becky G. Bruce ,  Michael D. Snyder ,  Gary L. Whisenhunt ,  Kumar Gala

发明人： Becky G. Bruce ,  Michael D. Snyder ,  Gary L. Whisenhunt ,  Kumar Gala

IPC分类号： G06F12/02

CPC分类号： G06F12/0284

摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.

摘要翻译： 处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置 具有第三个地址空间。 处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块 被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。 存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。

公开(公告)号：US4403726A

公开(公告)日：1983-09-13

申请号：US141608

申请日：1980-04-18

申请人： Michael D. Snyder ,  Crawford A. Matson

发明人： Michael D. Snyder ,  Crawford A. Matson

IPC分类号： B23P19/00 ,  H05K13/04 ,  B25B5/08

CPC分类号： H05K13/0421 ,  B23P19/001 ,  Y10T29/5142

摘要： Under direction of a machine controller, an endless chain conveyor is incrementally passed by a plurality of loader heads. The loader heads receive a series of components taped on a reel supplied substrate, sever individual taped components from the supply, and load the individual taped components onto clip carriers of the endless conveyor, on command, in a preferred sequence. The clip carrier mounted components are then indexed past a cutter assembly for trimming the lengths of the leads and removing the substrate, and a positioning disc assembly for positioning the components in the clip carriers before being passed to a rotary transfer assembly. The rotary transfer assembly removes individual components from the conveyor and rotates to an unload position above a linear loader, which laterally transfers the components from the rotary transfer to an insert head assembly. At the insert head assembly, the components are oriented and inserted by their leads into the holes of a printed circuit board for clinching by a clinch mechanism. Any components still left on the conveyor after it passes the rotary transfer assembly are removed by a chain unloader.

摘要翻译： 在机器控制器的方向下，循环链式输送机由多个装载机头递增地通过。 装载机头部接收一系列被卷绕在卷轴供应的基板上的部件，从供应装置中分离出各个胶带部件，并按照优先顺序将各个胶带部件装载到环形输送机的夹子载体上。 然后，夹具承载件安装的部件被转过通过切割器组件以修剪引线的长度和移除基板;以及定位盘组件，用于在传递到旋转传递组件之前将部件定位在夹子载体中。 旋转传递组件从输送机中移除各个部件，并且旋转到线性装载机上方的卸载位置，其将部件从旋转传递横向地传送到插入头组件。 在插入头组件中，组件被引导件定位并插入印刷电路板的孔中，用于通过夹紧机构夹紧。 通过旋转传递组件后仍然留在输送机上的任何部件都被链式卸料机除去。

公开(公告)号：US4282965A

公开(公告)日：1981-08-11

申请号：US95514

申请日：1979-11-16

申请人： Erwin F. Bates ,  Michael D. Snyder

发明人： Erwin F. Bates ,  Michael D. Snyder

IPC分类号： B65G47/14 ,  B65G47/24

CPC分类号： B65G47/1492

摘要： A method and apparatus for feeding and orienting parts having at least one terminal depending from each body. The parts are fed with at least one terminal in sliding engagement along a guide rail. Misoriented parts are blown out of engagement with the guide rail by a fluid ejection means and recirculated for refeeding and orienting.

摘要翻译： 一种用于进给和定向具有至少一个端子的部件的方法和装置，所述端子依赖于每个主体。 这些部件沿着导轨以至少一个端子滑动接合。 通过流体喷射装置使偏心部件与导轨脱离接合，并再循环以供进料和定向。

公开(公告)号：US20120185678A1

公开(公告)日：2012-07-19

申请号：US13435123

申请日：2012-03-30

申请人： Becky Bruce ,  Giles R. Frazier ,  Bradly G. Frey ,  Kumar K. Gala ,  Cathy May ,  Michael D. Snyder ,  Gary Whisenhunt ,  James Xenidis

发明人： Becky Bruce ,  Giles R. Frazier ,  Bradly G. Frey ,  Kumar K. Gala ,  Cathy May ,  Michael D. Snyder ,  Gary Whisenhunt ,  James Xenidis

IPC分类号： G06F9/38

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3889

摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

摘要翻译： 用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找， 处理器核心内的缓冲区。 来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。 在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。 然后控制逻辑更新线程状态以指示线程被禁用。

公开(公告)号：US08156357B2

公开(公告)日：2012-04-10

申请号：US12360656

申请日：2009-01-27

申请人： Shayan Zhang ,  James D. Burnett ,  Prashant U. Kenkare ,  Hema Ramamurthy ,  Andrew C. Russell ,  Michael D. Snyder

发明人： Shayan Zhang ,  James D. Burnett ,  Prashant U. Kenkare ,  Hema Ramamurthy ,  Andrew C. Russell ,  Michael D. Snyder

IPC分类号： G06F1/32

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  G11C7/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.

摘要翻译： 当存储器的电源电压降低以降低功率和/或增加耐久性时，存储器就会失败。 当电源电压升高到原始值时，这些位变得正常工作。 随着电压降低，不使用包含非功能位的存储器部分。 许多内存可能保持功能，并保留使用。 当电压增加时，因为由于电源电压降低而不被使用的存储器部分可以被再次使用。 这在缓存中特别有用，其中由于电源电压降低引起的可用存储器的减少可以被实现为方式数量的减少。 因此，例如，当功率降低或耐力增加时，八路缓存可以简单地简化为四路高速缓存。