公开(公告)号：US07229889B2

公开(公告)日：2007-06-12

申请号：US10906881

申请日：2005-03-10

申请人： Steven J. Holmes ,  Charles W. Koburger, III ,  David V. Horak ,  Toshiharu Furukawa ,  Mark C. Hakey

发明人： Steven J. Holmes ,  Charles W. Koburger, III ,  David V. Horak ,  Toshiharu Furukawa ,  Mark C. Hakey

IPC分类号： H01L21/20

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795

摘要： A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.

摘要翻译： 提供了一种对半导体上的栅极导体进行金属镀覆的方法。 该方法包括在半导体上限定有机聚合物电镀心轴，激活有机聚合物电镀心轴的一个或多个位点，以及将种子层结合到一个或多个活化位点。 然后可以将金属导电材料电镀在种子层上以形成栅极导体。 还提供了其上镀有宽度在约1至约7纳米之间的栅极导体的半导体器件。

公开(公告)号：US06506653B1

公开(公告)日：2003-01-14

申请号：US09524677

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665

摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

摘要翻译： 提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。 此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。 这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。 以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。 优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。 沉积保形层并用掺杂剂注入。 执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

公开(公告)号：US06333533B1

公开(公告)日：2001-12-25

申请号：US09394964

申请日：1999-09-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky ,  Jack A. Mandelman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky ,  Jack A. Mandelman

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.

摘要翻译： 一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。 由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

公开(公告)号：US06258661B1

公开(公告)日：2001-07-10

申请号：US09651614

申请日：2000-08-30

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

IPC分类号： H01L27108

CPC分类号： H01L27/10885 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/743 ,  H01L27/10876

摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

摘要翻译： 本发明提供了通过利用其中沟槽区域中的掺杂剂材料扩散到半导体衬底中的激光退火步骤在半导体衬底中形成向外扩散位线的方法。 外扩散位线也可以利用离子注入步骤形成。

公开(公告)号：US07838943B2

公开(公告)日：2010-11-23

申请号：US11161146

申请日：2005-07-25

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/70

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US07601205B2

公开(公告)日：2009-10-13

申请号：US12125442

申请日：2008-05-22

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： B03C3/60

CPC分类号： B03C3/41 ,  B03C3/60 ,  B03C2201/10 ,  Y10S977/742

摘要： An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further includes an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further include a metal layer over the carbon nanotube.

摘要翻译： 空气颗粒除尘器和空气过滤方法包括壳体单元; 住房单元中的第一个导体; 壳体单元中的第二导体; 和在第二导体上生长的碳纳米管。 优选地，第一导体与第二导体相对定位。 空气粒子除尘器还包括适于向壳体单元施加电场的电场源。 此外，碳纳米管适于使壳体单元中的气体电离，其中电离气体对位于壳体单元中的气体微粒进行充电，并且其中第一导体适于捕集带电气体微粒。 空气粒子沉淀器还可以包括在碳纳米管上的金属层。

公开(公告)号：US07528494B2

公开(公告)日：2009-05-05

申请号：US11266456

申请日：2005-11-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

摘要翻译： 制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。 还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。

公开(公告)号：US07504314B2

公开(公告)日：2009-03-17

申请号：US10907565

申请日：2005-04-06

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L29/93 ,  H01L21/76

CPC分类号： H01L21/76267 ,  H01L21/76243 ,  H01L21/76281 ,  H01L21/76283

摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

摘要翻译： 本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。 制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。 如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。 在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

公开(公告)号：US07491631B2

公开(公告)日：2009-02-17

申请号：US11757660

申请日：2007-06-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/425

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

摘要翻译： 一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。 制造该结构的方法包括：提供具有顶表面的基底; 在所述基板的顶表面上形成岛，所述岛的顶表面平行于所述基底的顶表面，所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入，所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入所述基板。

公开(公告)号：US20080286971A1

公开(公告)日：2008-11-20

申请号：US12186075

申请日：2008-08-05

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/311

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823828 ,  H01L21/823864

摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

摘要翻译： 用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。 牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。 心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。 侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。