公开(公告)号：US06387782B2

公开(公告)日：2002-05-14

申请号：US09875072

申请日：2001-06-06

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L21336

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

公开(公告)号：US07952149B2

公开(公告)日：2011-05-31

申请号：US10908442

申请日：2005-05-12

申请人： Omer H. Dokumaci ,  Oleg Gluschenkov

发明人： Omer H. Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L29/78

CPC分类号： H01L29/105 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/6659 ,  H01L29/66636

摘要： An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

摘要翻译： 提供了一种用于根据栅极长度控制半导体器件的有源区域中的净掺杂的装置和方法。 选择补偿掺杂剂是一种掺杂剂，其将电中和衬底中相反类型的掺杂剂。 通过以相对高的角度和高能量注入补偿掺杂剂，补偿掺杂剂将进入并通过用于短通道的栅极区域，并且对栅极区域内的总掺杂剂浓度几乎没有或没有影响。 在通道长度较长的情况下，高注入角度和高注入能量使得补偿掺杂剂落入通道内，从而中和相反类型的掺杂剂的一部分。

公开(公告)号：US07859061B2

公开(公告)日：2010-12-28

申请号：US12538111

申请日：2009-08-08

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US07682887B2

公开(公告)日：2010-03-23

申请号：US11557509

申请日：2006-11-08

申请人： Omer H. Dokumaci ,  Woo-Hyeong Lee

发明人： Omer H. Dokumaci ,  Woo-Hyeong Lee

IPC分类号： H01L21/338

CPC分类号： H01L29/66606 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

摘要： Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.

摘要翻译： 公开了形成具有高迁移率通道的晶体管的方法和结果。 在一个实施例中，该方法包括提供包括栅极材料区域和栅极电介质的栅电极，栅电极位于硅衬底中的沟道上方。 在栅电极周围形成电介质层，并且从栅极电极去除栅极材料区域和栅极电介质，以形成露出源极/漏极延伸部分的硅衬底的一部分的开口。 然后在开口中形成高迁移率半导体材料，即具有大于掺杂硅的载流子迁移率的高迁移率半导体材料，使得其侧向接触源极/漏极延伸部。 然后可以重新形成栅极电介质和栅极材料区域。 本发明消除了形成用于相关技术方法的高迁移率通道材料之后的高温步骤。

公开(公告)号：US07453123B2

公开(公告)日：2008-11-18

申请号：US11676030

申请日：2007-02-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07205185B2

公开(公告)日：2007-04-17

申请号：US10663471

申请日：2003-09-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US07026247B2

公开(公告)日：2006-04-11

申请号：US10696686

申请日：2003-10-28

申请人： Omer H. Dokumaci ,  Oleg Gluschenkov

发明人： Omer H. Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L21/461

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/82385 ,  Y10S438/947

摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.

摘要翻译： 提供了用于制造微结构的自校正蚀刻（SCORE）工艺。 本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。 或者，通过应用SCORE可以显着地减少在打印期间产生的硬掩模特征的CD变化。 因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。 因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。

公开(公告)号：US06806534B2

公开(公告)日：2004-10-19

申请号：US10342423

申请日：2003-01-14

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66553

摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

公开(公告)号：US06803315B2

公开(公告)日：2004-10-12

申请号：US10212938

申请日：2002-08-05

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21302

CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.

摘要翻译： 提供了一种用于阻挡来自FET器件的栅电极的植入物的方法。 形成覆盖基板和栅极电极堆叠的第一平坦化膜。 第一平面化膜通过抛光或自平面平坦化。 为了通过HDP沉积或者在材料上使用旋涂，该膜是自平面化的。 在需要抛光的情况下，第一平面化膜通过抛光进行平坦化，直到栅电极的顶部露出。 在第一平面化膜的上表面的水平面下方蚀刻栅电极。 然后沉积第二平坦化膜和抛光剂的覆盖层以将其平坦化至暴露第一平坦化膜的水平，将第二平坦化膜形成为覆盖栅极顶表面的注入块。 取下第一个平面化膜。 通过使用注入块将掺杂剂注入衬底来形成反向掺杂区域，以阻止掺杂剂注入到栅电极中。 注入块在植入反向掺杂区域期间保护FET的栅电极免受不希望的注入杂质。 第一平面化膜由选自HDP（高密度等离子体）氧化硅和HDP氮化硅的材料，包含ONO的层间介电层材料和光致抗蚀剂组成。 栅电极由选自多晶硅和金属的材料组成。 第二平面化膜包括诸如HDP氧化物，HDP氮化物和包括ARC的有机层的材料。 第二平面化膜包括与第一平坦化膜不同的材料。

公开(公告)号：US06569781B1

公开(公告)日：2003-05-27

申请号：US10054078

申请日：2002-01-22

申请人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

IPC分类号： H01L21265

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/518

摘要： A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

摘要翻译： 在硅衬底上形成氧化物层的方法包括在硅衬底上形成牺牲氧化物层，将氮注入到硅衬底中，退火具有注入氮的硅衬底，从硅衬底去除牺牲氧化层， 硅衬底上的氧化物层。 植入硅中的氮的剂量优选高于1e14cm31 2.退火过程优选在约550℃至约1000℃的温度下进行约1秒至约2秒的时间 小时。