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    Memory Devices Having an Embedded Resistance Memory with Metal-Oxygen Compound
    61.
    发明申请
    Memory Devices Having an Embedded Resistance Memory with Metal-Oxygen Compound 有权
    具有金属氧化合物嵌入式电阻记忆体的存储器件

    公开(公告)号：US20100301330A1

    公开(公告)日：2010-12-02

    申请号：US12855630

    申请日：2010-08-12

    申请人： ChiaHua Ho ,  Erh-Kun Lai

    发明人： ChiaHua Ho ,  Erh-Kun Lai

    IPC分类号： H01L29/68

    CPC分类号： H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

    摘要翻译： 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

    GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE
    62.
    发明申请
    GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE 有权
    基于金属氧化物电阻的半导体存储器件

    公开(公告)号：US20100277967A1

    公开(公告)日：2010-11-04

    申请号：US12431983

    申请日：2009-04-29

    申请人： MING-DAOU LEE ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

    发明人： MING-DAOU LEE ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

    IPC分类号： G11C11/00 ,  H01L47/00

    CPC分类号： H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

    摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

    摘要翻译： 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

    ONO formation of semiconductor memory device and method of fabricating the same
    63.
    发明授权
    ONO formation of semiconductor memory device and method of fabricating the same 有权
    ONO形成半导体存储器件及其制造方法

    公开(公告)号：US07763935B2

    公开(公告)日：2010-07-27

    申请号：US11159269

    申请日：2005-06-23

    申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

    摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

    Non-volatile memory device having a nitride-oxide dielectric layer
    64.
    发明授权
    Non-volatile memory device having a nitride-oxide dielectric layer 有权
    具有氮化物 - 氧化物电介质层的非易失性存储器件

    公开(公告)号：US07763927B2

    公开(公告)日：2010-07-27

    申请号：US11300813

    申请日：2005-12-15

    申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

    发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

    摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

    摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

    GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY
    65.
    发明申请
    GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY 有权
    半导体器件的门结构和形成字线结构和存储器的方法

    公开(公告)号：US20100148239A1

    公开(公告)日：2010-06-17

    申请号：US12333359

    申请日：2008-12-12

    申请人： Erh-Kun Lai ,  Hang-Ting Lue

    发明人： Erh-Kun Lai ,  Hang-Ting Lue

    IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/768

    CPC分类号： H01L27/11568 ,  H01L21/28282

    摘要： A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.

    摘要翻译： 提供了一种用于半导体器件的栅极结构。 栅极结构包括导电结构。 绝缘地设置在衬底上的导电结构包括中间部分和两个间隔部分。 中间部分具有第一表面和两个第二表面。 第一表面位于两个第二表面之间。 两个间隔部分分别连接到中间部分的两个第二表面。 两个间隔部分的每个的宽度从上到下逐渐增加。

    Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
    68.
    发明授权
    Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer 有权
    具有氧化物 - 氧化物 - 氧化物（ONO）顶部介电层的非易失性存储器半导体器件

    公开(公告)号：US07576386B2

    公开(公告)日：2009-08-18

    申请号：US11197668

    申请日：2005-08-04

    申请人： Hang-Ting Lue ,  Erh-Kun Lai

    发明人： Hang-Ting Lue ,  Erh-Kun Lai

    IPC分类号： H01L29/94

    CPC分类号： H01L29/792 ,  H01L29/513

    摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.

    摘要翻译： 非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域 源极和漏极区域之间的硅衬底。该电池包括形成在衬底的主表面上的底部氧化物层。 底部氧化物层设置在靠近阱区域的主表面的一部分上。 电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。 电介质隧道层包括第一氧化物层，氮化物层和第二氧化物层。 擦除NVM单元包括施加正栅极电压以从栅极注入孔。

    Asymmetric floating gate NAND flash memory
    69.
    发明授权
    Asymmetric floating gate NAND flash memory 有权
    非对称浮栅NAND闪存

    公开(公告)号：US07560762B2

    公开(公告)日：2009-07-14

    申请号：US11209437

    申请日：2005-08-23

    申请人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L29/80

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

    摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

    摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。 给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。 因此，浮置栅极下的反相通道可以作为源极/漏极。 结果，存储器件不需要浅结或辅助栅。 此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。