公开(公告)号：US08488362B2

公开(公告)日：2013-07-16

申请号：US12431983

申请日：2009-04-29

申请人： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

发明人： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

IPC分类号： G11C11/00

CPC分类号： H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

摘要翻译： 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

公开(公告)号：US08067762B2

公开(公告)日：2011-11-29

申请号：US11560723

申请日：2006-11-16

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

摘要： A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

摘要翻译： 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

公开(公告)号：US08022489B2

公开(公告)日：2011-09-20

申请号：US11134155

申请日：2005-05-20

申请人： Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/788 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112

CPC分类号： H01L27/115 ,  G11C16/0408 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/515

摘要： An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.

摘要翻译： 空气隧道浮动栅极存储单元包括限定在衬底上的空气通道。 在空气隧道上定义第一多晶硅层（浮栅）。 氧化物层设置在第一多晶硅层上，使得氧化物层覆盖第一多晶硅层并限定空气通道的侧壁。 用作字线的第二多晶硅层被定义在氧化物层上。 还公开了一种制造空气通道浮动栅极存储单元的方法。 在衬底上形成牺牲层。 在牺牲层上形成第一多晶硅层。 在第一多晶硅层上沉积氧化物层，使得氧化物层覆盖第一多晶硅层并限定牺牲层的侧壁。 使用热磷酸（H 3 PO 4）浸渍来蚀刻掉牺牲层以形成空气通道。

公开(公告)号：US20110189819A1

公开(公告)日：2011-08-04

申请号：US13083450

申请日：2011-04-08

申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8239

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US07943920B2

公开(公告)日：2011-05-17

申请号：US12836304

申请日：2010-07-14

申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/04

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US07816661B2

公开(公告)日：2010-10-19

申请号：US11562122

申请日：2006-11-21

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/06 ,  H01L47/00

CPC分类号： H01L45/144 ,  G11C13/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1293 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.

摘要翻译： 存储器件包括：第一电极元件，其大体呈平面形式，具有内部接触表面。 然后存在与第一电极元件间隔开的圆柱形盖层，以及具有与第一电极接触表面和盖层接触的接触表面的相变元件，其中相变元件的横向尺寸小于 的第一电极元件和圆柱形盖层。 第二电极元件延伸穿过盖层以与相变元件接触。 与介电填充材料构成的盖层对准的侧壁在第一电极元件和盖层之间延伸，使得相变元件，第一电极元件的接触表面和侧壁限定气体充满的热 隔离单元邻近相变元件。

公开(公告)号：US07777215B2

公开(公告)日：2010-08-17

申请号：US12176183

申请日：2008-07-18

申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US20100148142A1

公开(公告)日：2010-06-17

申请号：US12332837

申请日：2008-12-11

申请人： WEI-CHIH CHIEN ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： WEI-CHIH CHIEN ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/329 ,  H01L45/00

CPC分类号： G11C17/16 ,  H01L27/101 ,  H01L27/1021

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括第一电极和第二电极。 存储器件还包括二极管和包含氧化铝和氧化铜的抗熔丝金属氧化物存储元件。 二极管和金属氧化物存储元件电连接在第一电极和第二电极之间。

公开(公告)号：US07718989B2

公开(公告)日：2010-05-18

申请号：US11617542

申请日：2006-12-28

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L29/02

CPC分类号： H01L45/122 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

摘要翻译： 存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件 材料。 因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。 此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔 在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口 在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

公开(公告)号：US07709334B2

公开(公告)日：2010-05-04

申请号：US11425959

申请日：2006-06-22

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

摘要翻译： 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。 该器件可以配置为NAND操作。