公开(公告)号：US20190221609A1

公开(公告)日：2019-07-18

申请号：US16245783

申请日：2019-01-11

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kevin CONLEY ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/12 ,  H01L21/768 ,  H01F10/32 ,  G11C11/16 ,  H01F41/34

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/34 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.

公开(公告)号：US20190140019A1

公开(公告)日：2019-05-09

申请号：US16183956

申请日：2018-11-08

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD).

公开(公告)号：US20190103555A1

公开(公告)日：2019-04-04

申请号：US16194523

申请日：2018-11-19

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Kenneth H. SMITH ,  Moazzem HOSSAIN ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L21/3213 ,  H01L21/768 ,  H01L43/08 ,  H01L43/02 ,  H01L21/285 ,  H01L27/22

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US20190103554A1

公开(公告)日：2019-04-04

申请号：US16107543

申请日：2018-08-21

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin A. Deshpande ,  Kerry Joseph Nagel

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US20190043921A1

公开(公告)日：2019-02-07

申请号：US16143088

申请日：2018-09-26

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Sanjeev AGGARWAL ,  Kerry Joseph NAGEL ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20160260894A1

公开(公告)日：2016-09-08

申请号：US15142721

申请日：2016-04-29

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  G01R33/00 ,  H01L27/22 ,  G01R33/09 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US20160104835A1

公开(公告)日：2016-04-14

申请号：US14954075

申请日：2015-11-30

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  G01R33/09 ,  G01R33/00

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。