公开(公告)号：US20050122778A1

公开(公告)日：2005-06-09

申请号：US11033776

申请日：2005-01-12

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/34

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

公开(公告)号：US06865114B2

公开(公告)日：2005-03-08

申请号：US10372626

申请日：2003-02-20

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/16

Abstract: A word line selector for selecting word lines of an array of semiconductor memory cells formed in a doped semiconductor region of a semiconductor substrate comprises a plurality of word line drivers responsive to word line selection signals. Each word line driver is associated with a respective word line for driving the word line to prescribed word line electric potentials, depending on an operation to be conducted on the array of memory cells, in accordance with the word line selection signal.

Abstract translation: 用于选择形成在半导体衬底的掺杂半导体区域中的半导体存储单元阵列的字线的字线选择器包括响应于字线选择信号的多个字线驱动器。 根据字线选择信号，每个字线驱动器与用于将字线驱动到规定字线电位的相应字线相关联，取决于要对存储器单元阵列进行的操作。

公开(公告)号：US06668303B2

公开(公告)日：2003-12-23

申请号：US10057768

申请日：2002-01-24

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G06F1200

CPC classification number: G11C16/3418

Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory including at least one two-dimensional array of memory cells containing a plurality of individually erasable and programmable memory pages. Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying the content of said memory page and submitting a portion of the two-dimensional array to a refresh procedure. The refresh procedure includes detecting memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

公开(公告)号：US06618315B2

公开(公告)日：2003-09-09

申请号：US10057769

申请日：2002-01-24

Applicant: Federico Pio ,  Enrico Gomiero

Inventor： Federico Pio ,  Enrico Gomiero

IPC: G11C700

CPC classification number: G11C16/08 ,  G11C7/18

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets each one containing a second number of columns equal to or higher than the first number, memory cells belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection circuits are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.

公开(公告)号：US06473341B1

公开(公告)日：2002-10-29

申请号：US09625122

申请日：2000-07-25

Applicant: Enrico Gomiero ,  Federico Pio

Inventor： Enrico Gomiero ,  Federico Pio

IPC: G11C1604

CPC classification number: G11C16/12

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Abstract translation: 编程方法包括在写入单元时向所选单元的源极提供截止电压。 考虑到身体效应，截止电压是大于最大写入单元的阈值电压的绝对值（即最耗尽的单元）的幅度的正电压。 例如，截止电压可以比大多数写入单元的阈值电压的绝对值大1V。 有利的是，截止电压可以是5-6V; 为了考虑过程，供应和温度变化，截止电压可以是7-8V。编程方法有利地适用于具有划分的源极线的EEPROM存储器件，以便将截止电压仅施加到寻址字节 或字节，或包含寻址字节的页面。

公开(公告)号：US06278163B1

公开(公告)日：2001-08-21

申请号：US09224939

申请日：1998-12-31

Applicant: Federico Pio ,  Carlo Riva

Inventor： Federico Pio ,  Carlo Riva

IPC: H01L31062

CPC classification number: H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

Abstract translation: 集成在具有第一类型导电性的半导体衬底中的HV晶体管，包括在相应的漏极和源极区域之间包括的栅极区域，并且其中至少所述漏极区域被轻掺杂第二类型的导电性。 漏极区域包括具有第二类型导电性的接触区域，但是其重新掺杂，接触焊盘从该区域延伸。

公开(公告)号：US06255163B1

公开(公告)日：2001-07-03

申请号：US09330540

申请日：1999-06-11

Applicant: Nicola Zatelli ,  Cesare Clementi ,  Carlo Cremonesi ,  Federico Pio

Inventor： Nicola Zatelli ,  Cesare Clementi ,  Carlo Cremonesi ,  Federico Pio

IPC: H01L21336

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11543

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Abstract translation: 通过在选择晶体管本身的源极和漏极区域处的N型注入来增加选择晶体管的驱动能力。 这种植入方便地在自对准蚀刻结束时制作，使用相同的自对准蚀刻掩模来定义存储元件的控制栅极区域和浮动栅极区域，保持电路区域被电路掩模覆盖。

公开(公告)号：US5818760A

公开(公告)日：1998-10-06

申请号：US871226

申请日：1997-06-09

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

公开(公告)号：US5597750A

公开(公告)日：1997-01-28

申请号：US474735

申请日：1995-06-07

Applicant: Federico Pio ,  Carlo Riva ,  Silvia Lucherini

Inventor： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

Abstract translation: 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

公开(公告)号：US5393684A

公开(公告)日：1995-02-28

申请号：US988474

申请日：1992-12-10

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract translation: 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。