公开(公告)号：US09177951B2

公开(公告)日：2015-11-03

申请号：US14148221

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract translation: 三维静电放电（ESD）半导体器件与三维非ESD半导体器件一起制造。 例如，ESD二极管和FinFET制造在相同的体半导体衬底上。 衬底合并技术用于衬底的ESD部分中以形成双宽度鳍片，其上可以使ESD器件更大以处理更多的电流。

公开(公告)号：US20210036108A1

公开(公告)日：2021-02-04

申请号：US16526529

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Srikanth Balaji Samavedam

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.

公开(公告)号：US10833183B2

公开(公告)日：2020-11-10

申请号：US16177877

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joshua Dillon ,  Siva P. Adusumilli ,  Jagar Singh ,  Anthony Stamper ,  Laura Schutz

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/872

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

公开(公告)号：US10832842B2

公开(公告)日：2020-11-10

申请号：US16550431

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F5/06 ,  H01F5/00 ,  H01F17/00 ,  H01L49/02

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US20200035785A1

公开(公告)日：2020-01-30

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US20200020631A1

公开(公告)日：2020-01-16

申请号：US16578844

申请日：2019-09-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

公开(公告)号：US10510662B2

公开(公告)日：2019-12-17

申请号：US15805282

申请日：2017-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L21/76 ,  H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3105

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

公开(公告)号：US20190312109A1

公开(公告)日：2019-10-10

申请号：US15946281

申请日：2018-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Heimanu Niebojewski ,  Jagar Singh

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/324 ,  H01L21/84

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is formed that includes first and second semiconductor layers, and a gate structure is formed that is arranged over the first and second semiconductor layers. First and second source/drain regions are formed in which the second source/drain region is separated from the first source/drain region by the channel region. The first semiconductor layer is composed of a semiconductor material having a first carrier mobility, and the second semiconductor layer is composed of a semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US10290698B2

公开(公告)日：2019-05-14

申请号：US15437057

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/76 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.

公开(公告)号：US20190139892A1

公开(公告)日：2019-05-09

申请号：US15805282

申请日：2017-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.