公开(公告)号：US09542987B2

公开(公告)日：2017-01-10

申请号：US15012798

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Vinayak Bharat Naik ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: G11C11/15 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit is defined on the substrate. The cell selector unit includes at least one select transistor. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled to the selector unit. The MTJ element includes a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers. A spin-orbit-torque (SOT) layer is coupled to the selector unit and is in direct contact with the free layer. A strain induced layer is coupled to a digital line (DL) and is in direct contact with the SOT layer. When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer.

Abstract translation: 公开了用于形成存储单元的存储单元和方法。 存储单元包括由存储单元区限定的衬底。 在基板上限定单元选择器单元。 单元选择器单元包括至少一个选择晶体管。 包括磁性隧道结（MTJ）元件的存储元件被耦合到选择器单元。 MTJ元件包括夹在固定层和自由层之间的自由层，固定层和隧道屏障。 自旋轨道转矩（SOT）层耦合到选择器单元并与自由层直接接触。 应变感应层耦合到数字线（DL）并与SOT层直接接触。 当DL被激活时，施加到应变感应层的电场在SOT层上引起应变。

公开(公告)号：US20240162365A1

公开(公告)日：2024-05-16

申请号：US17984564

申请日：2022-11-10

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Khee Yong Lim ,  Kian Ming Tan ,  Kiok Boone Elgin Quek

IPC: H01L31/107 ,  H01L31/0224 ,  H01L31/028 ,  H01L31/18

CPC classification number: H01L31/1075 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/1804

Abstract: Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure comprises a substrate having a first conductivity type, a first semiconductor layer that defines an absorption region of the avalanche photodetector, a dielectric layer between the first semiconductor layer and the substrate, a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer, and a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate. The second semiconductor layer defines a multiplication region of the avalanche photodetector.

公开(公告)号：US11774402B2

公开(公告)日：2023-10-03

申请号：US17699219

申请日：2022-03-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01N27/414 ,  H01L29/16 ,  H01L29/04

CPC classification number: G01N27/4148 ,  G01N27/4145 ,  H01L29/04 ,  H01L29/16

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

公开(公告)号：US11659709B2

公开(公告)日：2023-05-23

申请号：US16999067

申请日：2020-08-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Juan Boon Tan ,  Kiok Boone Elgin Quek ,  Eng Huat Toh

IPC: H01L27/11521 ,  H01L29/66 ,  H01L49/02 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L28/60 ,  H01L29/0653 ,  H01L29/66825 ,  H01L29/7884

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

公开(公告)号：US20220359580A1

公开(公告)日：2022-11-10

申请号：US17307323

申请日：2021-05-04

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Kiok Boone Elgin Quek ,  Kien Seen Daniel Chong ,  Jing Hua Michelle Tng

IPC: H01L27/146

Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor substrate having a top surface, a semiconductor layer on the top surface of the semiconductor substrate, a light-absorbing layer on a portion of the semiconductor layer, and a doped region in the portion of the semiconductor layer. The doped region is positioned in the portion of the semiconductor layer adjacent to the light-absorbing layer.

公开(公告)号：US11320417B2

公开(公告)日：2022-05-03

申请号：US16505733

申请日：2019-07-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: G01N33/487 ,  G01N27/447

Abstract: In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.

公开(公告)号：US11313827B2

公开(公告)日：2022-04-26

申请号：US16455772

申请日：2019-06-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01N27/41 ,  G01N27/414 ,  H01L29/16 ,  H01L29/04

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

公开(公告)号：US20220093765A1

公开(公告)日：2022-03-24

申请号：US17026436

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.

公开(公告)号：US11245067B2

公开(公告)日：2022-02-08

申请号：US16671613

申请日：2019-11-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Ruchil Kumar Jain ,  Kiok Boone Elgin Quek

IPC: H01L43/06 ,  H01L27/22 ,  G01R33/00 ,  H01L43/14

Abstract: Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

公开(公告)号：US20220037349A1

公开(公告)日：2022-02-03

申请号：US16940586

申请日：2020-07-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/11568 ,  H01L29/792

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.