公开(公告)号：US11888031B2

公开(公告)日：2024-01-30

申请号：US17537564

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737 ,  H01L29/735

CPC classification number: H01L29/1008 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737

Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.

公开(公告)号：US11804541B2

公开(公告)日：2023-10-31

申请号：US17578011

申请日：2022-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

公开(公告)号：US11777019B2

公开(公告)日：2023-10-03

申请号：US17586862

申请日：2022-01-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/737 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/735

Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

公开(公告)号：US20230307238A1

公开(公告)日：2023-09-28

申请号：US17701759

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Man Gu ,  Eric S. Kozarsky

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/84

CPC classification number: H01L21/28052 ,  H01L27/1203 ,  H01L29/45 ,  H01L29/4933 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/84

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

公开(公告)号：US11749727B2

公开(公告)日：2023-09-05

申请号：US17546200

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu ,  Alexander Derrickson

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/401 ,  H01L29/66242 ,  H01L29/7371

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.

公开(公告)号：US20230261088A1

公开(公告)日：2023-08-17

申请号：US17669584

申请日：2022-02-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Hong Yu ,  Jianwei Peng ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/285

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/42392 ,  H01L29/78696

Abstract: Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

公开(公告)号：US11705508B2

公开(公告)日：2023-07-18

申请号：US17398479

申请日：2021-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/7851

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US20230120538A1

公开(公告)日：2023-04-20

申请号：US17680434

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.

公开(公告)号：US20230102573A1

公开(公告)日：2023-03-30

申请号：US17586862

申请日：2022-01-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/735 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

公开(公告)号：US11610965B2

公开(公告)日：2023-03-21

申请号：US17185236

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.