公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

申请人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

发明人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC分类号： H01L2972

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06437404B1

公开(公告)日：2002-08-20

申请号：US09636239

申请日：2000-08-10

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L2701

CPC分类号： H01L29/78696 ,  H01L21/26533 ,  H01L21/28079 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78603

摘要： A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

摘要翻译： 完全耗尽的绝缘体上半导体（SOI）晶体管器件具有SOI衬底，其具有相对于衬底的顶表面具有不均匀深度的掩埋绝缘体层，所述掩埋绝缘体层具有靠近顶表面的较浅部分比 层的深部分。 栅极形成在绝缘体层的顶表面和浅部之间的薄半导体层上。 源极和漏极区域形成在栅极的任一侧上，源极和漏极区域分别位于掩埋绝缘体层的深部之一的顶部。 源极和漏极区域因此具有比薄的半导体层更大的厚度。 形成在源区和漏区的厚硅化物区具有低寄生电阻。 制造晶体管器件的方法包括在SOI衬底上形成虚拟栅极结构，并且使用虚拟栅极结构来控制注入的深度以形成不均匀深度的掩埋绝缘体层。

公开(公告)号：US06369429B1

公开(公告)日：2002-04-09

申请号：US09641727

申请日：2000-08-21

申请人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

发明人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC分类号： H01L2352

CPC分类号： H01L21/28518 ,  H01L21/28568

摘要： Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

摘要翻译： 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US06362055B1

公开(公告)日：2002-03-26

申请号：US09144527

申请日：1998-08-31

申请人： Ming-Ren Lin ,  Bin Yu

发明人： Ming-Ren Lin ,  Bin Yu

IPC分类号： H01L218234

摘要： A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

公开(公告)号：US06271132B1

公开(公告)日：2001-08-07

申请号：US09303693

申请日：1999-05-03

申请人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

发明人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7833

摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

摘要翻译： 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高k栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06238960B1

公开(公告)日：2001-05-29

申请号：US09483400

申请日：2000-01-14

申请人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

发明人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

摘要翻译： 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

申请人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

发明人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC分类号： H01L27088

CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

摘要： A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

摘要翻译： 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06207553B1

公开(公告)日：2001-03-27

申请号：US09237258

申请日：1999-01-26

申请人： Matthew S. Buynoski ,  Ming-Ren Lin

发明人： Matthew S. Buynoski ,  Ming-Ren Lin

IPC分类号： H01L214763

CPC分类号： H01L21/76885 ,  H01L21/32135

摘要： Submicron-dimensioned metallization patterns are formed on a substrate surface by a photo-activated selective, anisotropic etching process, wherein selective portions of a metal layer are exposed to collimated UV passing through a pattern of submicron-sized openings in an overlying exposure mask. At least one photo-activatable etching material contained in a gas flowed through the space between the substrate surface and the mask selectively and anisotropically etches the exposed portions of the metal layer in thereby avoiding numerous masking and etching steps as in conventional photolithographic methodology. The inventive method is of particular utility in performing multi-level, in-laid, “back-end” metallization processing of high-density integrated circuit semiconductor devices.

摘要翻译： 通过光激活的选择性各向异性蚀刻工艺在衬底表面上形成亚微米尺寸的金属化图案，其中金属层的选择部分暴露于准直的UV穿过覆盖的曝光掩模中的亚微米尺寸的开口图案。 包含在通过衬底表面和掩模之间的空间中流动的气体中的至少一种可光致活化的蚀刻材料选择性地并且各向异性地蚀刻金属层的暴露部分，从而避免了如常规光刻方法中的许多掩模和蚀刻步骤。 本发明的方法在执行高密度集成电路半导体器件的多层次的，内置的“后端”金属化处理中是特别有用的。

公开(公告)号：US06190980B1

公开(公告)日：2001-02-20

申请号：US09150874

申请日：1998-09-10

申请人： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

发明人： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/66537

摘要： A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

摘要翻译： 在ULSI致密结构中进行凹槽，晕圈和源极/漏极延伸的倾斜注入的方法。 该方法克服了在密集结构中的阴影效应，在ULSI电路中使用大角度倾斜植入技术的过程极限。 通过插入氮化物间隔物限定氧化层中的开口，并且通过插入氮化物间隔物来部分地填充以限定实际的门窗开口。 小角度倾斜植入技术具有大角度倾斜植入物的等效掺杂效应，并避开了大角度植入法中发生的最大角度限制（thetaMAX）。 小角度倾斜植入技术还自动提供袋/晕/延伸植入物到装置的门的自对准。

公开(公告)号：US06180487B2

公开(公告)日：2001-01-30

申请号：US09427134

申请日：1999-10-25

申请人： Ming-Ren Lin

发明人： Ming-Ren Lin

IPC分类号： H01L21762

CPC分类号： H01L21/76243

摘要： In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving the steps of providing a monocrystalline silicon substrate; patterning a mask over the monocrystalline silicon substrate thereby exposing a portion of the monocrystalline silicon substrate; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon substrate; removing the mask from the monocrystalline silicon substrate; implanting a second dosage of oxygen atoms without using an implantation mask in the monocrystalline silicon substrate; and annealing the oxygen implanted monocrystalline silicon substrate to provide the Silicon-on-Insulator substrate. In another embodiment, the present invention relates to a Silicon-on-Insulator structure containing a monocrystalline silicon layer; a buried oxide layer over the monocrystalline silicon layer, the buried oxide layer including a first region having a first thickness and a second region having a second thickness, wherein the first thickness is from about 30% to about 70% smaller than the second thickness; a silicon device layer over the buried oxide layer; and a heat generating device on the silicon device layer and positioned over the first region of the buried oxide layer.

摘要翻译： 在一个实施方案中，本发明涉及一种形成绝缘体上硅衬底的方法，其包括提供单晶硅衬底的步骤; 在单晶硅衬底上形成掩模，从而暴露出单晶硅衬底的一部分; 在单晶硅衬底的暴露部分中注入第一剂量的氧原子; 从单晶硅衬底去除掩模; 在单晶硅衬底中不使用注入掩模来注入第二剂量的氧原子; 以及退火氧注入的单晶硅衬底以提供绝缘体上硅绝缘体衬底。 在另一个实施方案中，本发明涉及一种含有单晶硅层的绝缘体上硅结构， 在单晶硅层上的掩埋氧化层，所述掩埋氧化物层包括具有第一厚度的第一区域和具有第二厚度的第二区域，其中所述第一厚度比所述第二厚度小约30％至约70％; 掩埋氧化物层上的硅器件层; 以及在所述硅器件层上并位于所述掩埋氧化物层的所述第一区域上方的发热器件。