公开(公告)号：US08886897B2

公开(公告)日：2014-11-11

申请号：US11505835

申请日：2006-08-18

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C5/04

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

公开(公告)号：US08766711B2

公开(公告)日：2014-07-01

申请号：US13345112

申请日：2012-01-06

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： H03K3/01

CPC分类号： H02M3/155 ,  H03K17/6877

摘要： A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

摘要翻译： 开关电路器件具有第一晶体管，其具有耦合到高电位端子的漏极，耦合到低电位电源的源极和驱动电路，其响应于第一晶体管输出到第一晶体管的栅极 输入控制信号，具有高于第一晶体管的阈值电压的电位的脉冲和低电位电源的电位，其中驱动电路具有第一反相器，该第一反相器包括设置在栅极和源极之间的第二晶体管 第一晶体管，其中当第一晶体管由于脉冲而从接通变为截止时，第二晶体管导通并使第一晶体管的栅极和源极短路。

公开(公告)号：US20120091986A1

公开(公告)日：2012-04-19

申请号：US13181710

申请日：2011-07-13

申请人： Yoshihiro Takemae ,  Tsutomu Hosoda

发明人： Yoshihiro Takemae ,  Tsutomu Hosoda

IPC分类号： G05F3/08 ,  H01L27/088

CPC分类号： H01L27/088 ,  G05F3/08 ,  H01L21/8252 ,  H01L27/0605

摘要： A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes.

摘要翻译： 半导体器件包括：第一晶体管，包括在衬底上形成的GaN基半导体层叠结构，在半导体层叠结构上具有多个第一指状物的第一栅电极，沿着第一指状物设置的多个第一漏电极， 沿着第一指状物设置的多个第一源电极; 包括半导体层叠结构的第二晶体管，在半导体堆叠结构上具有多个第二指状物的第二栅极电极，沿着第二指状物设置的第二漏极电极以及沿着第二指状物设置的多个第二源极电极; 漏极焊盘，设置在所述第一漏电极之上或之下，并且耦合到所述第一漏电极; 源极焊盘，设置在所述第二源电极之上或之下，并且耦合到所述第二源电极; 以及耦合到第一源极和第二漏极的公共焊盘。

公开(公告)号：US20070091678A1

公开(公告)日：2007-04-26

申请号：US11583129

申请日：2006-10-19

申请人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

发明人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

IPC分类号： G11C16/06

CPC分类号： G11C16/32 ,  G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411 ,  G11C2207/104

摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

摘要翻译： 易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。 存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。 因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。 结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

公开(公告)号：US06744300B2

公开(公告)日：2004-06-01

申请号：US10277707

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H01J1982

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06492846B1

公开(公告)日：2002-12-10

申请号：US09474702

申请日：1999-12-29

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K300

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过这种结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US6075393A

公开(公告)日：2000-06-13

申请号：US998478

申请日：1997-12-29

申请人： Hiroyoshi Tomita ,  Yoshihiro Takemae

发明人： Hiroyoshi Tomita ,  Yoshihiro Takemae

IPC分类号： G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  H03K5/135 ,  H03L7/081 ,  H03L7/00

CPC分类号： G11C7/222 ,  G11C7/1078 ,  G11C7/22 ,  H03L7/0812

摘要： A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.

摘要翻译： 与系统一起使用的时钟同步半导体器件系统和半导体器件具有在适当的定时执行的读和写操作，而不增加时钟的类型或布线的数量。 该系统包括与时钟同步操作的多个半导体器件。 其中一个半导体器件用作用于产生与其余半导体器件的控制有关的信号的控制器。 用于将时钟发送到每个半导体器件的时钟信号线与其他信号线并联布置。 当远离控制器的位置处的时钟源被布置在读取数据从其余半导体器件到达控制器时不会产生任何偏斜。 通过每个存储器中包括的输入定时调整电路调整每个存储器从控制器检索写数据的定时，从而允许每个存储器在最佳定时检索写数据。

公开(公告)号：US5896347A

公开(公告)日：1999-04-20

申请号：US925458

申请日：1997-09-08

申请人： Hiroyoshi Tomita ,  Yoshihiro Takemae

发明人： Hiroyoshi Tomita ,  Yoshihiro Takemae

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03L7/00 ,  G11C8/00

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.

摘要翻译： 公开了一种使用同步存储器并且由于在从SDRAM读取数据时所需的余量减小而以更高速度工作的半导体存储器系统，以及用于实现其的半导体存储器件。 半导体存储器系统包括至少一个半导体存储器件和用于对半导体存储器件进行数据输入/输出的控制器件，其中控制器件与第一同步信号同步地输出要存储在半导体存储器件中的数据 控制装置输出，半导体存储装置与半导体存储装置输出的第二同步信号同步地输出输出数据。 在这样构成的半导体存储器系统中，半导体存储器件包括在输出数据和第二同步信号之间引入规定相位角的输出移相电路，并且在半导体存储器件侧进行输出数据和 第二同步信号相对于彼此精确地以规定的相位角被控制，并且使得在接收数据选通信号时可以在控制器侧立即产生锁存脉冲。

公开(公告)号：US5404328A

公开(公告)日：1995-04-04

申请号：US262352

申请日：1994-06-20

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C29/00 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/045 ,  G11C29/83 ,  G11C2216/10

摘要： A memory cell for storing data includes a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into the memory cell and outputting the data, and a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of the first field effect transistor, and a drain connected to the drain of the first field effect transistor. The second field effect transistor has a conduction type opposite to that of the first field effect transistor. The memory cell has a capacitor which has a first terminal receiving a select signal for identifying the memory cell, and a second terminal connected to the floating gates of the first and second field effect transistors. The data is stored in the floating gates of the first and second field effect transistors.

摘要翻译： 用于存储数据的存储单元包括：第一场效应晶体管，其具有接收第一电压的源极，浮置栅极和漏极接收要写入存储单元的数据并输出数据;以及第二场效应晶体管，具有源极 接收第二电压，连接到第一场效应晶体管的浮置栅极的浮动栅极和连接到第一场效应晶体管的漏极的漏极。 第二场效应晶体管具有与第一场效应晶体管相反的导通类型。 存储单元具有电容器，其具有接收用于识别存储单元的选择信号的第一端子和连接到第一和第二场效应晶体管的浮置栅极的第二端子。 数据存储在第一和第二场效应晶体管的浮置栅极中。

公开(公告)号：US5179536A

公开(公告)日：1993-01-12

申请号：US794705

申请日：1991-11-20

申请人： Yasushi Kasa ,  Yoshihiro Takemae ,  Masanori Nagasawa ,  Yuji Arayama ,  Akira Terui ,  Sunao Araki

发明人： Yasushi Kasa ,  Yoshihiro Takemae ,  Masanori Nagasawa ,  Yuji Arayama ,  Akira Terui ,  Sunao Araki

IPC分类号： G06F11/00 ,  G11C11/407 ,  G11C17/16 ,  G11C29/00

CPC分类号： G11C29/76 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822 ,  G06F11/006

摘要： A semiconductor memory device comprises a first memory comprising memory cells for prestoring fixed data, a decoder for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part including a third memory for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

摘要翻译： 半导体存储器件包括：第一存储器，包括用于预先存储固定数据的存储器单元;解码器，用于解码输入地址，并且用于基于解码输入地址从第一存储器读出固定数据;第二存储器，用于存储与 预先存储在第一存储器的有缺陷的存储单元中，其中第二存储器包括可编程非易失性存储器单元，识别部分包括第三存储器，用于存储第一存储器的每个有缺陷的存储器单元的冗余地址，以区分是否 所述输入地址与所述冗余地址一致，并且当所述输入地址与所述冗余地址一致时输出鉴别信号，以及选择单元，提供从所述第一和第二存储器读出的数据，以正常地输出从所述第一存储器读出的数据 并且当从th接收到鉴别信号时，选择性地输出来自第二存储器的数据 识别部分。