摘要:
The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
摘要:
An input shaft 10 is connected rotationally with an intermediary shaft 20 through a connecting drive gear GCV, a connecting first idle gear GC1, a connecting second idle gear GC2 and a connecting driven gear GCN. A fourth speed drive gear G4V, which is formed in a one-piece body with a reverse drive gear GRV, is provided rotatably over the input shaft 10, and a third speed drive gear G3V is provided rotatably over the intermediary shaft 20. Both the third speed drive gear G3V and the fourth speed drive gear G4V mesh with a third and fourth speed driven gear G34N, which is provided rotatably over an output shaft 40. Also, a reverse driven gear GRN, which is connected rotationally with the reverse drive gear GRV through a reverse idle gear GRI, is provided rotatably over the output shaft 40. Either the third and fourth speed driven gear G34N or the reverse driven gear GRN is connected to the output shaft 40 by a selective clutch CTD.
摘要:
A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
摘要:
A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
摘要:
An oil sump 44 and a second oil supply passage 45, which are to lead lubrication oil from a first oil supply passage 43 to where lubrication is needed, i.e., to gears and a clutch, are formed in a sun gear 21, which has a sufficient strength as a torque transmission member. In comparison with another case where an oil sump and an oil supply passage are provided in a relatively thin member such as a sleeve 3, the unfavorable effect of stress concentration around the oiling aperture and of deterioration of strength from the reduced thickness can be greatly minimized. In addition, the fabrication of the oil sump and the oil supply passage is much easier and cost-effective than if they were to be provided in a thinner member.
摘要:
An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
摘要:
The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.
摘要:
An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values; has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.
摘要:
A planetary gear transmission typically for use on automobiles has first, second, and third planetary gear trains arranged coaxially with each other and each having elements including a sun gear, a carrier, and a ring gear. Two of the elements of each of the first, second, and third planetary gear trains are directly or disengageably coupled to elements of the other planetary gear trains. The transmission also has three clutch means and two brake means for selectively establishing a power transmitting path from an input shaft to an output gear member through the first, second, and third planetary gear trains. At least one of the first, second, and third planetary gear trains comprises a double-pinion planetary gear train, one of the sun gear and the carrier of the double-pinion planetary gear train being coupled to the input shaft and the other being nonrotatably fixed. The elements of the first, second, and third planetary gear trains are corotatably coupled into first, second, third, fourth, and fifth rotational members in a speed diagram, the third and fifth rotatable members being coupled to the input member, the fourth rotational member being coupled to the output member and. The carrier of the double-pinion planetary gear train may be coupled to the input shaft, and the sun gear thereof may be nonrotatably fixed.
摘要:
A planetary gear transmission typically for use on automobiles has first, second, and third planetary gear trains arranged coaxially with each other and each having elements including a sun gear, a carrier, and a ring gear. Two of the elements of each of the first, second, and third planetary gear trains are directly or disengageably coupled to elements of the other planetary gear trains. The transmission also has two clutch means and three brake means for selectively establishing a power transmitting path from an input shaft to an output gear member through the first, second, and third planetary gear trains. The first planetary gear train comprises a double-pinion planetary gear train, one of the sun gear and the carrier of the double-pinion planetary gear train being coupled to the input shaft and the other being disengageably coupled to a stationary member. The elements of the first, second, and third planetary gear trains are corotatably coupled into first, second, third fourth, and fifth rotational members in a speed diagram, the third and fifth rotatable members being coupled to the input member, the fourth rotational member being coupled to the output member.