公开(公告)号：US10336896B2

公开(公告)日：2019-07-02

申请号：US14787041

申请日：2014-04-23

申请人： Jie Zheng ,  Qiang Chen ,  Chao Zhao

发明人： Jie Zheng ,  Qiang Chen ,  Chao Zhao

IPC分类号： C12C11/02 ,  C08L33/26 ,  C08B37/00 ,  C08L5/12 ,  C08J3/075 ,  C08L5/00

摘要： A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.

公开(公告)号：US20160083574A1

公开(公告)日：2016-03-24

申请号：US14787041

申请日：2014-04-23

申请人： Jie Zheng ,  Qiang Chen ,  Chao Zhao

发明人： Jie Zheng ,  Qiang Chen ,  Chao Zhao

IPC分类号： C08L33/26 ,  C08L5/12

CPC分类号： C08L33/26 ,  C08B37/0039 ,  C08J3/075 ,  C08J2305/12 ,  C08J2333/26 ,  C08J2405/12 ,  C08J2433/26 ,  C08L5/00 ,  C08L5/12 ,  C08L33/10

摘要： A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.

摘要翻译： 提供了在单锅合成中形成具有高可回收和机械性质的杂化物理和化学交联双网络水凝胶的方法。 该方法包括以下步骤：将水凝胶前体反应物合并成单个罐。 水凝胶前体反应物包括水; 多糖; 甲基丙烯酸酯单体; 紫外线引发剂; 和化学交联剂。 接下来将水凝胶前体反应物加热到高于多糖的熔点的温度，并保持该温度，直到多糖处于溶胶状态。 然后将单釜冷却至低于多糖的凝胶化点的温度，并保持该温度以形成第一网络。 此后，通过紫外线引发剂发生甲基丙烯酸酯单体的光引发聚合以形成第二网络。

公开(公告)号：US09202890B2

公开(公告)日：2015-12-01

申请号：US14119862

申请日：2012-12-12

申请人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

发明人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L21/8249 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28123 ,  H01L29/4232 ,  H01L29/78

摘要： A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

摘要翻译： 提供了一种在门最后工艺中制造虚拟栅极的方法。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。 相应地，还提供了最后进程中的虚拟门。

公开(公告)号：US09049061B2

公开(公告)日：2015-06-02

申请号：US13640733

申请日：2012-04-11

申请人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

发明人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC分类号： H01L27/092 ,  H01L21/265 ,  H04L21/02

CPC分类号： H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

摘要： This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

摘要翻译： 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

公开(公告)号：US09024435B2

公开(公告)日：2015-05-05

申请号：US13379347

申请日：2011-08-12

申请人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L23/34 ,  H01L23/522 ,  H01L23/467 ,  H01L23/473

CPC分类号： H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

摘要翻译： 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US20130273669A1

公开(公告)日：2013-10-17

申请号：US13698283

申请日：2012-06-12

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： H01L21/306

CPC分类号： H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

摘要翻译： 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二介电隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化方法的均匀性的方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20130213434A1

公开(公告)日：2013-08-22

申请号：US13497768

申请日：2011-11-28

申请人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

发明人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC分类号： H01L21/02

CPC分类号： H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

摘要： A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

摘要翻译： 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US08420492B2

公开(公告)日：2013-04-16

申请号：US13143591

申请日：2011-01-27

申请人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

摘要翻译： 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

公开(公告)号：US20130020618A1

公开(公告)日：2013-01-24

申请号：US13379347

申请日：2011-08-12

申请人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L21/50

CPC分类号： H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

摘要翻译： 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US20120244784A1

公开(公告)日：2012-09-27

申请号：US13142714

申请日：2011-04-11

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： B24B53/017 ,  B24B1/00

CPC分类号： B24B37/015 ,  B24B37/20 ,  B24B53/017 ,  Y02P80/30

摘要： A chemical-mechanical polishing tool and a method for preheating the same are disclosed. The chemical-mechanical polishing tool includes: a polishing pad, a deionized water supply channel, a polishing slurry supply channel and a polishing pad conditioner; and the chemical-mechanical polishing tool further includes: a heating apparatus, adapted to heat DI water fed to the DI water supply channel; a temperature sensor, arranged close to the polishing pad to measure a temperature of the polishing pad; and a preheating control system, connected to the temperature sensor, and adapted to control the DI water supply channel to spray the heated DI water to the polishing pad, and when the temperature measured by the temperature sensor is equal to or higher than a predetermined temperature, to close the DI water supply channel, control the polishing slurry supply channel to spray polishing slurry to the polishing pad, and startup the polishing pad conditioner to dress the polishing pad. The invention can reduce the consumption of polishing consumables by the chemical-mechanical polishing tool during preheating, thereby reducing production cost.

摘要翻译： 公开了一种化学机械抛光工具及其预热方法。 化学机械抛光工具包括：抛光垫，去离子水供应通道，抛光浆料供应通道和抛光垫调节剂; 并且所述化学机械抛光工具还包括：加热设备，其适于加热供给到所述DI供水通道的去离子水; 温度传感器，布置在抛光垫附近以测量抛光垫的温度; 以及预热控制系统，其连接到所述温度传感器，并且适于控制所述DI供水通道将所述加热的去离子水喷射到所述抛光垫，并且当所述温度传感器测量的温度等于或高于预定温度 关闭DI供水通道，控制抛光浆料供应通道将抛光浆料抛光到抛光垫上，并启动抛光垫调节剂来修整抛光垫。 本发明可以通过化学机械抛光工具在预热期间减少抛光耗材的消耗，从而降低生产成本。