公开(公告)号：US20250112187A1

公开(公告)日：2025-04-03

申请号：US18374578

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Thomas Sounart ,  YI Shi

IPC: H01L23/00 ,  H01L23/538

Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.

公开(公告)号：US20250112186A1

公开(公告)日：2025-04-03

申请号：US18374574

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Thomas Sounart ,  Kimin Jun ,  Wenhao Li

IPC: H01L23/00

Abstract: A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.

公开(公告)号：US20250112181A1

公开(公告)日：2025-04-03

申请号：US18374522

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Yi Shi ,  Kimin Jun ,  Adel Elsherbini ,  Thomas Sounart ,  Wenhao Li ,  Xavier Brun

IPC: H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.

公开(公告)号：US20250112173A1

公开(公告)日：2025-04-03

申请号：US18374577

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Thomas Sounart ,  Yi Shi ,  Wenhao Li

IPC: H01L23/00 ,  H01L23/31

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

公开(公告)号：US20250112077A1

公开(公告)日：2025-04-03

申请号：US18478391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Andrey Vyatskikh ,  Adel Elsherbini ,  Brandon M. Rawlings ,  Tushar Kanti Talukdar ,  Thomas L. Sounart ,  Kimin Jun ,  Johanna Swan ,  Grant M. Kloster ,  Carlos Bedoya Arroyave

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.

公开(公告)号：US12199018B2

公开(公告)日：2025-01-14

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H05K1/11

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US20240413031A1

公开(公告)日：2024-12-12

申请号：US18207808

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Chandru Periasamy ,  Jagat Shakya ,  Joshua Jeremy Cardiel Rivera ,  Jaime A. Sanchez ,  Devesh Srivastava ,  Feras Eid ,  Matthew Zeman ,  Xavier F. Brun ,  Nabankur Deb

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/367 ,  H01L23/373

Abstract: An electronic device and associated methods are disclosed. Electronic devices are shown that include a semiconductor die and a patterned layer connected to a backside of the die. Electronic devices are shown that include a pattern of elements across a patterned layer that varies across the backside of a die. Electronic devices are further shown that include a compliant filler within elements in a patterned layer.

公开(公告)号：US12155133B2

公开(公告)日：2024-11-26

申请号：US18133361

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Sasha N. Oster ,  Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Aleksandar Aleksov

IPC: H01Q1/38 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/52 ,  H01Q9/04 ,  H01Q19/22 ,  H01L23/367

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

公开(公告)号：US12119291B2

公开(公告)日：2024-10-15

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/32 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49894 ,  H01L2224/08225 ,  H01L2224/32225

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US12040307B2

公开(公告)日：2024-07-16

申请号：US16887126

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Georgios Dogiamis

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/81222 ,  H01L2224/81815

Abstract: Magnetic structures incorporated into integrated circuit assemblies. In some examples, the magnetic structures may enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates.