中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

84 records (took 0.032 seconds)

    System, apparatus and method for prefetching physical pages in a processor
    61.
    发明授权
    System, apparatus and method for prefetching physical pages in a processor 有权

    公开(公告)号：US12019553B2

    公开(公告)日：2024-06-25

    申请号：US17130696

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Hanna Alam ,  Joseph Nuzman

    IPC: G06F12/0862 ,  G06F12/084

    CPC classification number: G06F12/0862 ,  G06F12/084 ,  G06F2212/6028

    Abstract: In one embodiment, a processor includes: one or more execution circuits to execute instructions; a stream prediction circuit coupled to the one or more execution circuits, the stream prediction circuit to receive demand requests for information and, based at least in part on the demand requests, generate a page prefetch hint for a first page; and a prefetcher circuit to generate first prefetch requests each for a cache line, the stream prediction circuit decoupled from the prefetcher circuit. Other embodiments are described and claimed.

    Apparatuses, methods, and systems for instructions to compartmentalize code
    66.
    发明授权
    Apparatuses, methods, and systems for instructions to compartmentalize code 有权

    公开(公告)号：US11556341B2

    公开(公告)日：2023-01-17

    申请号：US17341068

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

    Spatial and temporal merging of remote atomic operations
    67.
    发明授权
    Spatial and temporal merging of remote atomic operations 有权

    公开(公告)号：US11500636B2

    公开(公告)日：2022-11-15

    申请号：US16799619

    申请日：2020-02-24

    Applicant: Intel Corporation

    Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

    IPC: G06F9/30 ,  G06F12/0875

    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

    DATA TAINTING TO MITIGATE SPECULATION VULNERABILITIES
    68.
    发明申请
    DATA TAINTING TO MITIGATE SPECULATION VULNERABILITIES 有权

    公开(公告)号：US20220207149A1

    公开(公告)日：2022-06-30

    申请号：US17134347

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Jason W. Brandt ,  Joseph Nuzman ,  Asit Mallick ,  Carlos Rozas

    IPC: G06F21/57 ,  G06F21/75 ,  G06F21/53

    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability detection hardware and execution hardware. The speculation vulnerability detection hardware is to detect vulnerability to a speculative execution attack and, in connection with a detection of vulnerability to a speculative execution attack, to provide an indication that data from a first operation is tainted. The execution hardware is to perform a second operation using the data if the second operation is to be performed non-speculatively and to prevent performance of the second operation if the second operation is to be performed speculatively and the data is tainted.

Patent Agency Ranking