公开(公告)号：US11639623B2

公开(公告)日：2023-05-02

申请号：US16859452

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/3218 ,  G06F1/3234 ,  E05D11/00 ,  H05K5/02

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US11538633B2

公开(公告)日：2022-12-27

申请号：US16306889

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01G4/224 ,  H01G4/005 ,  H01L23/16 ,  H01L49/02 ,  H05K1/02 ,  H05K3/28

Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

公开(公告)号：US11481001B2

公开(公告)日：2022-10-25

申请号：US17088620

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Chee Chun Yee ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim ,  Jeff Ku

IPC: G06F1/16

Abstract: According to the various examples, a dual display system having a first panel having a first display area, a second panel having a second display area, and a connector assembly, attached to the first and second panels, that is configured to enable the first and second panels to rotate around three-directional axes. The connector assembly includes an elongated member and a hinge assembly, which are configured for attachment to the first and second display panels. The present dual display system may have several functional modalities, including use as a desktop computer, a laptop computer, a tablet, and a panoramic display.

公开(公告)号：US20220337248A1

公开(公告)日：2022-10-20

申请号：US17856768

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： J-Wing Teh ,  Min Suet Lim ,  Lai Guan Tang ,  MD Altaf Hossain ,  Gregory Steinke

IPC: H03K19/17736 ,  H01L25/065 ,  H01L23/538 ,  H01L25/18

Abstract: Systems, methods, and devices are provided for configurable die-to-die communication between dies of an integrated circuit system using a programmable routing bridge. Such an integrated circuit system may include a first die on a substrate, a second die on the substrate, and a programmable routing bridge embedded in the substrate. The programmable routing bridge may be mounted to the first die and the second die and is configurable to transfer data between selectable points of the first die and selectable points of the second die.

公开(公告)号：US20220139814A1

公开(公告)日：2022-05-05

申请号：US17579186

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20220110214A1

公开(公告)日：2022-04-07

申请号：US17550746

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Martin M. Chang ,  Tin Poay Chuah ,  Eng Huat Goh ,  Chu Aun Lim ,  Min Suet Lim

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/30

Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.

公开(公告)号：US11211714B2

公开(公告)日：2021-12-28

申请号：US16462516

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Boon Ping Koh ,  Wil Choon Song ,  Khang Choong Yong

IPC: H01Q13/18 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q21/28

Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US11172581B2

公开(公告)日：2021-11-09

申请号：US16003970

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Tin Poay Chuah ,  Han Kung Chua

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

公开(公告)号：US20210183775A1

公开(公告)日：2021-06-17

申请号：US17024263

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  MD Altaf Hossain

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L49/02

Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.

公开(公告)号：US11030012B2

公开(公告)日：2021-06-08

申请号：US16146845

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06N3/04 ,  G06F11/30 ,  G06K9/62

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.