公开(公告)号：US20230200043A1

公开(公告)日：2023-06-22

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Julie ROLLINS ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230006067A1

公开(公告)日：2023-01-05

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Van H. LE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US20220216347A1

公开(公告)日：2022-07-07

申请号：US17701232

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Ashish AGRAWAL ,  Seung Hoon SUNG ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY

IPC: H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US20220199628A1

公开(公告)日：2022-06-23

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. SHARMA ,  Bernhard SELL ,  Chieh-Jen KU ,  Arnab SEN GUPTA ,  Matthew V. METZ ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG

IPC: H01L27/108 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US20220165735A1

公开(公告)日：2022-05-26

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US20200343379A1

公开(公告)日：2020-10-29

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Inanc MERIC ,  Benjamin CHU-KUNG

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312973A1

公开(公告)日：2020-10-01

申请号：US16651955

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

公开(公告)号：US20200227568A1

公开(公告)日：2020-07-16

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Abhishek A. SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Ravi PILLARISETTY ,  Miriam R. RESHOTKO ,  Shriram SHIVARAMAN ,  Li Huey TAN ,  Tristan A. TRONIC ,  Jack T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066912A1

公开(公告)日：2020-02-27

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/45

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.