公开(公告)号：US20210217698A1

公开(公告)日：2021-07-15

申请号：US16743247

申请日：2020-01-15

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  CHANRO PARK ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a fully aligned via design generally includes wide lines formed of copper and narrow lines formed of an alternative metal. The fully aligned vias are fabricated using a metal recess approach and the hybrid metal conductors can be fabricated using a selective deposition approach.

公开(公告)号：US11031339B2

公开(公告)日：2021-06-08

申请号：US16687833

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/48

Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.

公开(公告)号：US11024577B1

公开(公告)日：2021-06-01

申请号：US16746146

申请日：2020-01-17

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/525

Abstract: A method for manufacturing a semiconductor device includes forming first and second interconnect structures on an etch stop layer, wherein the second interconnect structure is spaced apart from the first interconnect structure. The etch stop layer extends between the first and second interconnect structures. In the method, part of the etch stop layer between the first and second interconnect structures is removed. The removing forms a first portion of the etch stop layer extending from under the first interconnect structure toward the second interconnect structure, and a second portion of the etch stop layer extending from under the second interconnect structure toward the first interconnect structure. The first and second portions are spaced apart from each other. A dielectric layer is formed which fills in the spaces between the first and second portions of the etch stop layer and between the first and second interconnect structures.

公开(公告)号：US11024344B2

公开(公告)日：2021-06-01

申请号：US16155447

申请日：2018-10-09

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: G11C5/06 ,  H01L45/00 ,  H01L27/22 ,  H01L43/08 ,  H01L29/78 ,  H01L43/12

Abstract: A conductive landing pad structure is formed utilizing a selective deposition process on a surface of an electrically conductive structure that is embedded in a first dielectric material layer. The conductive landing pad structure is located on an entirety of a surface of the electrically conductive structure and does not extend onto the first dielectric material layer. A conductive metal-containing structure is formed on a physically exposed surface of the conductive landing pad structure. During the formation of the conductive metal-containing structure which includes ion beam etching and/or a wet chemical etch, no conductive landing pad material particles re-deposit on the sidewalls of the conductive metal-containing structure.

公开(公告)号：US10998227B2

公开(公告)日：2021-05-04

申请号：US16732791

申请日：2020-01-02

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theodorus E Standaert

IPC: H01L21/8242 ,  H01L21/768 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/283 ,  H01L21/285 ,  H01L23/522 ,  H01L23/64

Abstract: A method for fabricating a capacitor structure is described. The method for metal insulator metal capacitor in an integrated circuit device includes forming a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is formed in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is formed over the extended top face of the bottom capacitor plate. A top capacitor plate is formed in a top, remainder portion of the trench on top of the high-k dielectric layer.

公开(公告)号：US10971398B2

公开(公告)日：2021-04-06

申请号：US16171440

申请日：2018-10-26

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Chih-Chao Yang

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes partially or completely cobalt filled openings. The cobalt metal is conformally deposited onto a noble metal layer and thermally annealed to reflow the cobalt metal and partially or completely fill the openings.

公开(公告)号：US20210091306A1

公开(公告)日：2021-03-25

申请号：US16582762

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lijuan Zou ,  John Arnold

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

公开(公告)号：US10957642B1

公开(公告)日：2021-03-23

申请号：US16576870

申请日：2019-09-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Chih-Chao Yang ,  Miaomiao Wang ,  Donald Francis Canaperi

IPC: H01L23/525

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse electrical contacts in the fuse stack structure.

公开(公告)号：US20210082714A1

公开(公告)日：2021-03-18

申请号：US16570316

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chanro Park ,  Chih-Chao Yang ,  Kangguo Cheng ,  Juntao Li

IPC: H01L21/311 ,  H01L23/532 ,  H01L21/768 ,  H01L21/033

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a method includes forming an interconnect structure having a base, a first conductive metal layer disposed on the base; and a first hardmask layer disposed on the first conductive metal layer. Metal lines are formed by subtractive etching. The metal lines have negative tapered sidewalk, and an opening is formed between adjacent metal lines. A first interlevel dielectric layer is deposited in the openings. A portion of the first interlevel dielectric layer is removed to form trench openings having positive tapered sidewalls. A dielectric layer is deposited in one of the openings. A liner layer and a second conducting metal layer are deposited in the other trench openings. The liner layer and the second conductive metal layer are recessed. A second hardmask layer is deposited on a top surface of the liner layer and the second conductive metal layer.

公开(公告)号：US10930520B2

公开(公告)日：2021-02-23

申请号：US16377975

申请日：2019-04-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L21/00 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized dielectric surface layer within the interconnect dielectric material. A metal layer is formed on the nitridized dielectric surface layer and then an anneal is performed to form a metal nitride layer between the metal layer and the nitridized dielectric surface layer. A portion of the originally deposited metal layer that is not reacted with the nitridized dielectric surface is then selectively removed and thereafter an electrical conducting structure is formed directly on the metal nitride layer that is present in the opening.