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公开(公告)号：US09240375B2
公开(公告)日：2016-01-19
申请号：US13931692
申请日：2013-06-28
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Edem Wornyo
IPC分类号： H03H11/40 , H01L23/525 , H01F17/02 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5256 , H01F17/0006 , H01F17/02 , H01F2017/0073 , H01L23/522 , H01L23/5227 , H01L23/5252 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
摘要翻译： 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。
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公开(公告)号：US20140097539A1
公开(公告)日：2014-04-10
申请号：US13928084
申请日：2013-06-26
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/7684 , H01L21/3212 , H01L23/522 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Pitch-dependent dishing and erosion following CMP treatment of copper features is quantitatively assessed by atomic force microscopy (AFM) and transmission electron microscopy (TEM). A new sequence of processing steps presented herein is used to prevent dishing and to reduce significantly the local pitch- and pattern density-induced CMP non-uniformity for copper metal lines having widths and spacing in the range of about 32-128 nm. The new process includes a partial copper deposition step followed by deposition of a silicon carbide/nitride (SiCxNy) blocking layer. A multi-step CMP process planarizes areas of the resulting irregular surface that have narrow features, while the blocking layer protects areas that have wide features.
摘要翻译： 通过原子力显微镜（AFM）和透射电子显微镜（TEM）定量评估CMP特征的CMP处理后的间距依赖性凹陷和侵蚀。 本文提出的新的处理步骤序列用于防止凹陷并显着减少具有宽度和间隔在约32-128nm范围内的铜金属线的局部间距和图案密度诱导的CMP不均匀性。 该新方法包括部分铜沉积步骤，然后沉积碳化硅/氮化物（SiC x N y）阻挡层。 多步CMP工艺平坦化具有窄特征的所得不规则表面的区域，而阻挡层保护具有广泛特征的区域。
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公开(公告)号：US20200058801A1
公开(公告)日：2020-02-20
申请号：US16591873
申请日：2019-10-03
发明人： Kangguo Cheng , Lawrence A. Clevenger , Carl Radens , Junli Wang , John H. Zhang
IPC分类号： H01L29/786 , H01L29/66 , H01L27/088 , H01L29/40 , H01L29/06 , H01L29/423 , H01L29/417
摘要： A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.
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公开(公告)号：US10546743B2
公开(公告)日：2020-01-28
申请号：US15874654
申请日：2018-01-18
发明人： John H. Zhang , Yann Mignot , Lawrence A. Clevenger , Carl Radens , Richard Stephen Wise , Yiheng Xu , Yannick Loquet , Hsueh-Chung Chen
IPC分类号： H01L21/02 , H01L23/522 , H01L23/532 , H01L21/311 , H01L21/768
摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.
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公开(公告)号：US10325777B2
公开(公告)日：2019-06-18
申请号：US15690540
申请日：2017-08-30
IPC分类号： H01L21/302 , H01L21/308 , H01L21/768 , H01L21/311 , H01L21/02
摘要： A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.
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公开(公告)号：US20190067024A1
公开(公告)日：2019-02-28
申请号：US15801039
申请日：2017-11-01
IPC分类号： H01L21/308 , H01L21/02 , H01L21/311 , H01L21/768
摘要： A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.
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公开(公告)号：US10109505B2
公开(公告)日：2018-10-23
申请号：US15424297
申请日：2017-02-03
发明人： John H. Zhang , Laertis Economikos , Adam Ticknor , Wei-Tsu Tseng
摘要： The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.
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68.发明授权公开(公告)号：US10026849B2
公开(公告)日：2018-07-17
申请号：US15259516
申请日：2016-09-08
IPC分类号： H01L21/8234 , H01L27/146 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/49
摘要： Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.
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公开(公告)号：US20180061817A1
公开(公告)日：2018-03-01
申请号：US15802525
申请日：2017-11-03
IPC分类号： H01L25/18 , H01L25/065 , H01L23/31 , H01L23/498 , H01L25/00 , H01L21/48 , H01L23/538
CPC分类号： H01L25/18 , H01L21/4846 , H01L23/13 , H01L23/15 , H01L23/3107 , H01L23/49827 , H01L23/49894 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555 , H01L2225/06568 , H01L2225/06572 , H01L2225/06589 , H01L2225/06593 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15156 , H01L2924/15313 , H01L2924/157
摘要： Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.
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公开(公告)号：US09646939B2
公开(公告)日：2017-05-09
申请号：US15090996
申请日：2016-04-05
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Byoung Youp Kim , Walter Kleemeier
IPC分类号： H01L21/4763 , H01L23/00 , H01L21/768 , H01L21/66 , H01L23/528 , H01L23/532 , H01L23/522
CPC分类号： H01L23/562 , H01L21/76805 , H01L21/76843 , H01L21/76897 , H01L22/12 , H01L22/14 , H01L22/32 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/528 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.
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