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61.发明授权公开(公告)号：US11282962B2
公开(公告)日：2022-03-22
申请号：US16841019
申请日：2020-04-06
IPC分类号： H01L29/94 , H01L29/78 , H01L21/28 , H01L29/49 , H01L21/02 , H01L29/06 , H01L21/8238 , H01L21/762
摘要： A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
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公开(公告)号：US20210074809A1
公开(公告)日：2021-03-11
申请号：US16567767
申请日：2019-09-11
摘要： A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
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公开(公告)号：US20200328121A1
公开(公告)日：2020-10-15
申请号：US16380487
申请日：2019-04-10
发明人： Yao Yao , Andrew M. Greene , Veeraraghavan S. Basker , Kangguo Cheng , Zhenxing Bi , Ruilong Xie
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/78
摘要： A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.
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公开(公告)号：US20200083334A1
公开(公告)日：2020-03-12
申请号：US16682361
申请日：2019-11-13
发明人： Kangguo Cheng , Andrew M. Greene , John R. Sporre , Peng Xu
IPC分类号： H01L29/40 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/8234
摘要： Methods of forming semiconductor devices include forming a lower dielectric layer, to a height below a height of a dummy gate hardmask disposed across multiple device regions, by forming a dielectric fill to the height of a dummy gate and etching the dielectric fill back. A dummy gate structure includes the dummy gate and the dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.
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公开(公告)号：US20200083088A1
公开(公告)日：2020-03-12
申请号：US16126521
申请日：2018-09-10
发明人： Huimei Zhou , Gen Tsutsui , Andrew M. Greene , Dechao Guo , Huiming Bu , Robert Robison , Veeraraghavan S. Basker , Reinaldo Vega
IPC分类号： H01L21/762 , H01L29/66 , H01L29/78 , H01L21/32
摘要： Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
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公开(公告)号：US10586706B2
公开(公告)日：2020-03-10
申请号：US16013214
申请日：2018-06-20
发明人： Andrew M. Greene , Ryan O. Jung , Ruilong Xie
IPC分类号： H01L21/336 , H01L21/283 , H01L29/66 , H01L21/28 , H01L21/311 , H01L27/02 , H01L21/033 , H01L21/3105
摘要： A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
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67.发明申请公开(公告)号：US20200052125A1
公开(公告)日：2020-02-13
申请号：US16059693
申请日：2018-08-09
IPC分类号： H01L29/78 , H01L21/28 , H01L29/49 , H01L29/06 , H01L21/8238 , H01L21/762 , H01L21/02
摘要： A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
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公开(公告)号：US20200044052A1
公开(公告)日：2020-02-06
申请号：US16599229
申请日：2019-10-11
IPC分类号： H01L29/66 , H01L21/768 , H01L21/027 , H01L27/088 , H01L21/306 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L21/308 , H01L21/762
摘要： A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
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公开(公告)号：US20200044051A1
公开(公告)日：2020-02-06
申请号：US16599164
申请日：2019-10-11
IPC分类号： H01L29/66 , H01L21/768 , H01L21/027 , H01L27/088 , H01L21/306 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L21/308 , H01L21/762
摘要： A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
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70.发明申请公开(公告)号：US20190172940A1
公开(公告)日：2019-06-06
申请号：US16267618
申请日：2019-02-05
发明人： Andrew M. Greene , Hong He , Sivananda K. Kanakasabapathy , Gauri Karve , Eric R. Miller , Pietro Montanini
摘要： FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
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