公开(公告)号：US10355690B2

公开(公告)日：2019-07-16

申请号：US15279273

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Siti Suhaila Mohd Yusof ,  Amit Kumar Srivastava ,  Lay Hock Khoo ,  Chin Boon Tear

IPC: H03K19/00 ,  H03K19/003 ,  G06F1/06 ,  G06F1/28

Abstract: An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.

公开(公告)号：US10339093B2

公开(公告)日：2019-07-02

申请号：US15083518

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

Abstract: An example system for side band communication can include a processor, a system-on-chip (SOC), and a repeater communicatively coupled to the processor and the SOC. The repeater can receive packets from a first transceiver. The repeater can also detect a pattern in the packets to identify a guest protocol. The repeater can further send the packets from the first transceiver to the SOC via a second transceiver based on the identified guest protocol.

公开(公告)号：US20190187929A1

公开(公告)日：2019-06-20

申请号：US15844964

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Sriram Balasubrahmanyam

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0679

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a device that includes an interface for communication with a host. The device includes components that can operate during at least one of read link training and duty cycle distortion compensation operation.

公开(公告)号：US20190087378A1

公开(公告)日：2019-03-21

申请号：US15706902

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Kenneth P. Foust

IPC: G06F13/42 ,  G06F13/38 ,  G06F1/26

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

公开(公告)号：US20190004590A1

公开(公告)日：2019-01-03

申请号：US15638049

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Chenchu Punnarao Bandi

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

公开(公告)号：US10128248B1

公开(公告)日：2018-11-13

申请号：US15650271

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Karthik Ns ,  Dharmaray Nedalgi ,  Vani Deshpande ,  Leonhard Heiss ,  Amit Kumar Srivastava

IPC: H01L29/76 ,  H01L27/105 ,  H01L23/58 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.

公开(公告)号：US20180293196A1

公开(公告)日：2018-10-11

申请号：US15483079

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Duane G. Quiet ,  Kenneth P. Foust

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: In one embodiment, a host controller includes a read controller to adjust internal clock timing based on a timer value associated with a first device and communicate information on an interconnect with the first device according to the adjusted clock timing. Other embodiments are described and claimed.

公开(公告)号：US10048731B2

公开(公告)日：2018-08-14

申请号：US14752225

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F1/00 ,  G06F1/26 ,  G06F13/42 ,  H02J7/04 ,  H02J7/00

Abstract: Techniques for mitigating voltage offsets are described herein. A method for mitigating voltage offset includes receiving, via a sensor, charging current information. The method also includes adjusting, via a common mode adjustment circuitry, a common mode voltage based on charging current information and a physical layer circuit mode.

公开(公告)号：US10042412B2

公开(公告)日：2018-08-07

申请号：US14563079

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Jia Jun Lee ,  Asad Azam

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42 ,  G06F9/4401

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.

公开(公告)号：US20180181531A1

公开(公告)日：2018-06-28

申请号：US15466315

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Duane G. Quiet ,  Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/36 ,  G06F13/4068 ,  G06F2213/0016

Abstract: Embodiments of the present disclosure may relate to an I3C bus master that is to identify that an I3C bus with which the I3C bus master is coupled is to enter a serial peripheral interface (SPI) high data rate (HDR) mode. The I3C bus master may be further to communicate, in accordance with the SPI HDR mode, with an SPI slave device via an I3C serial data (SDA) line, an I3C serial clock (SCL) line, and a selection line. Other embodiments may be described and/or claimed.