公开(公告)号：US20210375849A1

公开(公告)日：2021-12-02

申请号：US16887339

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Tahir Ghani

IPC: H01L25/18 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

公开(公告)号：US11189730B2

公开(公告)日：2021-11-30

申请号：US16649716

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US11171207B2

公开(公告)日：2021-11-09

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US11171057B2

公开(公告)日：2021-11-09

申请号：US16465490

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Chytra Pawashe ,  Anand S. Murthy ,  Daniel Pantuso ,  Tahir Ghani

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

公开(公告)号：US11164790B2

公开(公告)日：2021-11-02

申请号：US16632319

申请日：2017-08-17

Applicant: Intel Corporation

Inventor： Leonard P Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US20210335791A1

公开(公告)日：2021-10-28

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US11127841B2

公开(公告)日：2021-09-21

申请号：US16589936

申请日：2019-10-01

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Michael L. Hattendorf ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US11024713B2

公开(公告)日：2021-06-01

申请号：US16465758

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Glenn A. Glass ,  Harold W. Kennel ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/167 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

公开(公告)号：US11011550B2

公开(公告)日：2021-05-18

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/22 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US11004739B2

公开(公告)日：2021-05-11

申请号：US16219795

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.