公开(公告)号：US5604453A

公开(公告)日：1997-02-18

申请号：US301511

申请日：1994-09-07

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/003 ,  H03B1/00 ,  H03K19/094

CPC分类号： H03K19/00361

摘要： A device and method of reducing ground bounce using a CMOS driver 200. The driver includes a first CMOS pass gate 214 and a second CMOS pass gate 222. The first pass gate is used to drive the gate of a PMOS pull-up transistor 210, while the second pass gate is used to drive the gate of an NMOS pull-down transistor 218.

摘要翻译： 使用CMOS驱动器200减少接地反弹的装置和方法。驱动器包括第一CMOS通道栅极214和第二CMOS栅极222.第一栅极用于驱动PMOS上拉晶体管210的栅极， 而第二通道栅极用于驱动NMOS下拉晶体管218的栅极。

公开(公告)号：US5241224A

公开(公告)日：1993-08-31

申请号：US691640

申请日：1991-04-25

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

公开(公告)号：US5121006A

公开(公告)日：1992-06-09

申请号：US688252

申请日：1991-04-22

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/17712

摘要： A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.

公开(公告)号：US09559881B2

公开(公告)日：2017-01-31

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38 ,  H04L25/14

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US09081062B1

公开(公告)日：2015-07-14

申请号：US12870383

申请日：2010-08-27

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G11C29/00 ,  G01R31/3181 ,  G06F11/10

CPC分类号： G01R31/31816 ,  G06F11/106 ,  G06F11/1497 ,  G11C29/52 ,  G11C2029/0411 ,  H03K19/007 ,  H03K19/17764

摘要： Integrated circuits with memory error detection and correction (EDC) circuitry are provided. The EDC circuitry may include first and second data registers and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with a predetermined bit stream. If a soft error is detected, correct bits generated using a logic function associated with the predetermined bit stream may be written back to the selected frame. In another suitable arrangement, the EDC circuitry may include first and second registers, a mask register, and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with desired data. The mask register may be loaded with mask bits. If a soft error is detected, the correct bits may be written back to the selected frame if the corresponding mask bits are high.

摘要翻译： 提供了具有存储器错误检测和校正（EDC）电路的集成电路。 EDC电路可以包括第一和第二数据寄存器和比较器。 第一数据寄存器可以存储从所选帧读取的数据。 第二数据寄存器可以被加载预定的位流。 如果检测到软错误，则使用与预定比特流相关联的逻辑功能产生的正确比特可被写回所选择的帧。 在另一种合适的布置中，EDC电路可以包括第一和第二寄存器，掩码寄存器和比较器。 第一数据寄存器可以存储从所选帧读取的数据。 第二数据寄存器可以加载期望的数据。 掩码寄存器可以加载掩码位。 如果检测到软错误，则如果对应的掩码位为高，则可将正确的位写回所选择的帧。

公开(公告)号：US20120278906A1

公开(公告)日：2012-11-01

申请号：US13098074

申请日：2011-04-29

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G06F11/00 ,  G08B21/00

CPC分类号： G06F21/86 ,  G06F21/76 ,  H03K19/17768

摘要： Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

摘要翻译： 公开了用于防止可编程集成电路器件的篡改的系统和方法。 通常，可编程器件（如FPGA）具有两个操作阶段; 配置阶段和用户模式阶段。 为了防止可编程设备的篡改和/或反向工程，可以在任何操作阶段中采用各种防篡改技术，以在怀疑篡改之后禁用设备和/或擦除存储在设备上的敏感信息。 一种类型的篡改涉及用许多虚假配置尝试来轰炸设备以便解密加密的数据。 通过使用脏位和粘性错误计数器，设备可以跟踪发生的失败配置尝试次数，并在设备处于配置阶段怀疑篡改时启动防篡改操作。

公开(公告)号：US06366119B1

公开(公告)日：2002-04-02

申请号：US09677156

申请日：2000-10-02

申请人： Bruce B. Pedersen ,  John C. Costello

发明人： Bruce B. Pedersen ,  John C. Costello

IPC分类号： H03K19177

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17748

摘要： A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowed. This includes logically combining and registering the unborrowed product terms. The macrocell may include circuitry for feeding back to the AND array of the programmable logic device a combinatorial or registered signal of the macrocell, and also outputting such a combinatorial or registered signal from the macrocell. When a combinatorial signal is fed back, the register of the macrocell can be used for another signal of the macrocell.

摘要翻译： 用于可编程逻辑器件的宏单元包括用于允许相邻宏单元借用宏单元的各种数量的乘积项的电路。 宏单元可以继续充分利用其不被借用的产品术语。 这包括逻辑上组合和注册未管理的产品术语。 宏单元可以包括用于将可编程逻辑器件的AND阵列反馈给宏单元的组合或注册信号的电路，并且还从宏单元输出这样的组合或注册信号。 当反馈组合信号时，宏单元的寄存器可用于宏单元的另一个信号。

公开(公告)号：US06359468B1

公开(公告)日：2002-03-19

申请号：US09516865

申请日：2000-03-02

申请人： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

发明人： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

IPC分类号： H03K19177

CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

摘要： A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thence the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

摘要翻译： 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达该地区，每个地区的正确结果，然后计算和传播该组的正确进行。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。

公开(公告)号：US06323680B1

公开(公告)日：2001-11-27

申请号：US09517350

申请日：2000-03-02

申请人： Bruce B. Pedersen ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Vinson Chan ,  Stephen Brown ,  Tony Ngai ,  James Park

发明人： Bruce B. Pedersen ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Vinson Chan ,  Stephen Brown ,  Tony Ngai ,  James Park

IPC分类号： G06F738

CPC分类号： H03K19/17736 ,  G06F7/5443 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17732

摘要： A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.

摘要翻译： 可编程逻辑器件被配置为通过专用部件的每个逻辑区域中的提供来适应乘法，以形成和求和部分乘积。 专门的部件与逻辑区域的普通逻辑分开，并且它们的存在对普通逻辑功能的性能施加了很小的损失，同时通过最小化用于特定乘法运算的逻辑区域的数量来提高执行乘法的速度 并且还最小化设备的互连资源在这些区域之间传送信号的使用。

公开(公告)号：US06218859B1

公开(公告)日：2001-04-17

申请号：US09320007

申请日：1999-05-26

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17796

摘要： Disclosed is a programmable logic device (PLD) that includes logic cells that can be allocated among zones and are preferably allocated among four quadrants. I/O pins are permanently associated with a quadrant by placing the I/O pins along an exterior edge of that quadrant. Logic cells which are located in a quadrant are directly connected to I/O pins which are permanently associated with that quadrant. Even if additional logic cells are added to the PLD without changing the number of I/O pins, the I/O pins located along an exterior edge of a quadrant will still be directly connected to the logic cells in that quadrant. Thus, a user can determine whether use of a given I/O pin and logic cell, regardless of the number of logic cells in the PLD, will result in an inter-quadrant signal transmission delay.

摘要翻译： 公开了一种可编程逻辑器件（PLD），其包括可以在区域之间分配的逻辑单元，并且优选地在四个象限之间分配。 I / O引脚通过沿着该象限的外部边缘放置I / O引脚而永久地与象限相关联。 位于象限中的逻辑单元直接连接到与该象限永久关联的I / O引脚。 即使在不改变I / O引脚数量的情况下将额外的逻辑单元添加到PLD中，沿着象限的外部边缘定位的I / O引脚仍将直接连接到该象限中的逻辑单元。 因此，用户可以确定使用给定的I / O引脚和逻辑单元，无论PLD中的逻辑单元的数量如何，将导致象限间信号传输延迟。