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公开(公告)号：US06794627B2
公开(公告)日：2004-09-21
申请号：US10001438
申请日：2001-10-24
IPC分类号： H04N314
CPC分类号： H04N5/3765 , H04N5/347
摘要： An image sensor includes a plurality of active pixel sensors arranged in an array. Each active pixel sensor includes a photosensor that generates a sensor signal nominally indicative of an intensity of light incident on the photosensor and a follower-type amplifier that couples the sensor signal to an output of the active pixel sensor to provide a buffered sensor signal. A column line is provided for each column in the array, and each column line is coupled to the output of the active pixel sensors associated with that column. Row select signal generating circuitry is configured to substantially simultaneously select a set of plural particular rows of the array such that each of the active pixel sensors in the selected set of plural particular rows substantially simultaneously provides the buffered sensor signal for that pixel sensor to the column line for the column to which that pixel sensor belongs such that an output node of the column line indicates a collective output signal for the active pixel sensors in the selected set of plural particular rows, belonging to that column. Column select signal generating circuitry configured to substantially simultaneously select a set of plural particular columns of the array such that the output nodes for the selected plural particular columns are substantially simultaneously coupled to an output node of the image sensor.
摘要翻译： 图像传感器包括排列成阵列的多个有源像素传感器。 每个有源像素传感器包括一个光电传感器，它生成一个传感器信号，该传感器信号通常表示入射在光电传感器上的光的强度;以及跟随器型放大器，将传感器信号耦合到有源像素传感器的输出端，以提供缓冲的传感器信号。 为阵列中的每列提供列线，并且每个列线耦合到与该列相关联的有源像素传感器的输出。 行选择信号生成电路被配置为基本上同时选择阵列的多个特定行的集合，使得所选择的多个特定行中的每个有源像素传感器基本上同时向该列提供用于该像素传感器的缓冲的传感器信号 该像素传感器所属的列的行，使得列线的输出节点指示属于该列的所选择的多个特定行的集合中的活动像素传感器的集体输出信号。 列选择信号生成电路被配置为基本上同时选择阵列的多个特定列的集合，使得所选择的多个特定列的输出节点基本上同时耦合到图像传感器的输出节点。
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62.发明授权Intra-pixel frame storage element, array, and electronic shutter method suitable for electronic still camera applications 失效适用于电子静物照相机应用的像素内像素帧存储元件，阵列和电子快门方法公开(公告)号：US06369853B1
公开(公告)日：2002-04-09
申请号：US08969383
申请日：1997-11-13
IPC分类号： H04N314
CPC分类号： H04N5/353 , H01L27/14609 , H01L27/14623 , H01L27/14643 , H04N5/374 , H04N5/37452
摘要： A storage pixel sensor disposed on a semiconductor substrate comprises a capacitive storage element having a first terminal connected to a fixed potential and a second terminal. A photodiode has an anode connected to a first potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the second terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch. A light shield is disposed over portions of the semiconductor substrate comprising a circuit node including the second terminal of the semiconductor transfer switch, the second terminal of the capacitive storage element and the input of the semiconductor amplifier and to prevent substantially all photons from entering the circuit node. Structures are present for preventing substantially all minority carriers generated in the semiconductor substrate from entering the circuit node. A plurality of storage pixel sensors are disposed in an array.
摘要翻译： 设置在半导体衬底上的存储像素传感器包括具有连接到固定电位的第一端子和第二端子的电容性存储元件。 光电二极管具有连接到第一电位和阴极的阳极。 半导体复位开关具有连接到阴极的第一端子和连接到复位电位的第二端子。 半导体转移开关具有连接到阴极的第一端子和连接到电容性存储元件的第二端子的第二端子。 半导体放大器具有连接到电容性存储元件的输入端和输出端。 半导体复位开关和半导体转移开关各自具有连接到用于选择性地激活半导体复位开关和半导体转移开关的控制电路的控制元件。 光屏蔽设置在半导体衬底的包括电路节点的部分上的部分上，该电路节点包括半导体转移开关的第二端子，电容性存储元件的第二端子和半导体放大器的输入端，并且基本上防止所有的光子进入电路 节点。 存在用于防止在半导体衬底中产生的基本上所有少数载流子进入电路节点的结构。 多个存储像素传感器被布置成阵列。
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公开(公告)号：US6125053A
公开(公告)日：2000-09-26
申请号：US201677
申请日：1998-11-30
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10
摘要： A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
摘要翻译： pMOS EEPROM单元包括源极，漏极，通道，控制栅极和阱接触。 该器件是一个功能齐全的单元件p型浮栅MOSFET。 浮动栅极与阱接触重叠，并完全围绕漏极和源植入。 通过热电子注入将pMOS单元写入，使用内在反馈机制来写入模拟值。 通过在晶体管漏极处的空穴冲击电离在通道中产生热电子。 Fowler-Nordheim隧道消除了pMOS细胞。 隧道电压仅施加到阱以从浮动栅极隧道电子。 井源井漏井路口通过护环免受破坏。
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公开(公告)号：US06097432A
公开(公告)日：2000-08-01
申请号：US855938
申请日：1997-05-14
申请人： Carver A. Mead , Tobias Delbruck
发明人： Carver A. Mead , Tobias Delbruck
CPC分类号： G11C7/067 , G11C27/024
摘要： A sense amplifier comprises an input node and an output node. An input transistor has a gate connected to the input node, a source connected to a first supply voltage rail, and a drain. A cascode transistor has a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. The gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold. In a presently preferred embodiment of the present invention, the input transistor and the cascode transistor of the sense amplifier are wide and short, such that they operate in below threshold, whereas the load transistor is made long and relatively narrow, so that it operates above threshold.
摘要翻译： 感测放大器包括输入节点和输出节点。 输入晶体管具有连接到输入节点的栅极，连接到第一电源电压轨的源极和漏极。 共源共栅晶体管具有连接到共源共栅节点的栅极，连接到输入晶体管的漏极的源极和连接到输出节点的漏极。 负载晶体管具有连接到偏置节点的栅极，连接到输出节点的漏极和连接到第二电源电压轨的源极。 共源共栅晶体管和负载晶体管的栅极被偏置，使得输入晶体管和共源共栅晶体管在其阈值附近操作，并且负载晶体管被操作在阈值以上。 在本发明的当前优选实施例中，读出放大器的输入晶体管和共源共栅晶体管宽且短，使得它们工作在低于阈值，而负载晶体管被制造得很长而且相对较窄，使得其工作在上面 阈。
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65.发明授权Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range 失效制造具有高分辨率和宽动态范围的薄型多电容耦合非接触式成像仪的方法
公开(公告)号：US5837574A
公开(公告)日：1998-11-17
申请号：US789397
申请日：1997-01-29
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/146 , H01L21/8242
CPC分类号： H01L27/14609 , H01L21/823406 , H01L21/8238 , Y10S148/01 , Y10S148/124
摘要： A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.
摘要翻译： 电容耦合的非接触式成像器结构及其结构的制造方法产生包含在P型半导体材料中形成的N型集电极区域的光电晶体管。 在集电区域形成P型基极区域。 形成与P型基极区域的表面接触的n掺杂多晶硅发射极接触，使得在基极区域中形成n +外延区域作为成像器光电晶体管的发射极。 二氧化硅将基底区域的多晶硅发射极接触和暴露的表面与形成为覆盖整个基极区域的聚合物厚度约为500-600埃的厚度分离。
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公开(公告)号：US5627392A
公开(公告)日：1997-05-06
申请号：US399966
申请日：1995-03-07
IPC分类号： G11C27/00 , H01L29/788
CPC分类号： G11C27/005 , H01L29/7885
摘要： A silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.
摘要翻译： 提供了具有时变传递函数的硅MOS晶体管，其可以同时作为单晶体管模拟学习装置和单晶体管非易失性模拟存储器操作。 通过从N型MOS浮栅晶体管的完全绝缘的浮栅中添加或去除电子来实现时变传递函数。 晶体管具有电容耦合到浮动栅极的控制栅极; 从该控制栅极的角度看，晶体管的传递函数被修改。 电子通过Fowler-Nordheim隧道从浮动门去除。 电子通过热电子注入添加到浮动栅极。
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67.发明授权Capacitor coupled contactless imager with high resolution and wide dynamic range 失效电容耦合非接触式成像仪具有高分辨率和宽动态范围
公开(公告)号：US5552619A
公开(公告)日：1996-09-03
申请号：US436181
申请日：1995-05-10
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L27/105 , H01L27/146 , H01L31/11 , H01L31/06
CPC分类号： H01L31/1105 , H01L27/105 , Y10S148/124
摘要： A capacitor coupled contactless imager structure and a method of manufacturing the structure results is a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface to the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter contact and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.
摘要翻译： 电容耦合非接触式成像器结构及其结构制造方法是一种光电晶体管，其结构包括形成在P型半导体材料中的N型集电极区域。 在集电区域形成P型基极区域。 形成与P型基极区域的表面接触的n掺杂多晶硅发射极触点，使得在基极区域中形成n +外延区域作为光电晶体管的发射极。 二氧化硅将poly1发射极接触和暴露在基部区域的表面与部分覆盖基极区域的约3000-4000厚的poly2层分离; CMOS外围器件的栅极也是poly2。 基极区域上的poly2用作成像器结构的基极耦合电容器和行导体。 poly2电容器板的厚度允许使用常规技术进行掺杂，并且硅化以改善RC常数。
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公开(公告)号：US5541878A
公开(公告)日：1996-07-30
申请号：US267595
申请日：1994-06-27
CPC分类号： G05F3/247 , G05F1/468 , G05F3/24 , G11C11/56 , G11C11/5621 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator. During normal operation of the voltage reference circuit, the voltage comparator is configured as a follower amplifier to buffer the analog voltage output. During normal operation of the bias reference circuit, the current comparator is configured as a current mirror to buffer the analog current output.
摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电路，使得所有浮动栅极存储装置可以单独地或并行地编程到它们的目标电压。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 提供了具有轻掺杂漏极的晶体管结构，用于控制隧道结构。 电容器连接到每个浮动栅极节点以提供对注入结构的控制。 提供动态模拟存储元件以存储浮动栅极存储装置的目标电压。 提供一个比较器来监控浮动栅极电压和目标电压，并控制隧道和注入。 提供数字存储设备以静态存储比较器的输出。 在电压基准电路正常工作期间，电压比较器被配置为跟随放大器以缓冲模拟电压输出。 在偏置参考电路的正常工作期间，电流比较器被配置为电流镜以缓冲模拟电流输出。
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69.发明授权CMOS low-power, wide-linear-range, well-input differential and transconductance amplifiers 失效CMOS低功耗，宽线性范围，良好输入的差分和跨导放大器
公开(公告)号：US5463348A
公开(公告)日：1995-10-31
申请号：US281218
申请日：1994-07-27
申请人： Rahul Sarpeshkar , Carver A. Mead
发明人： Rahul Sarpeshkar , Carver A. Mead
CPC分类号： H03F3/45076 , H03F1/3211
摘要： A novel family of CMOS differential and transconductance amplifiers has wide input linear range and is suited for low power operation. The wide linear range is obtained by "widening the tanh", or decreasing the ratio of transconductance to bias current, by combining the three techniques of (a) using the well terminals of the input differential-pair transistors as the amplifier inputs; (b) using the feedback technique known as source degeneration; and (c) using the novel feedback technique of gate degeneration. According to one preferred embodiment of the present invention a compact transconductance amplifier having a linear range of .+-.1 V was achieved in an 11-transistor circuit with a DC-input operating range of 1 V-5 V in a low-power subthreshold CMOS technology in a standard 2 micron process.
摘要翻译： 一个新颖的CMOS差分和跨导放大器系列具有宽输入线性范围，适用于低功耗操作。 通过组合（a）使用输入差分对晶体管的阱端子作为放大器输入的三种技术，通过“拓宽tanh”或减小跨导与偏置电流的比率来获得宽的线性范围; （b）使用称为源变性的反馈技术; 和（c）使用门退化的新型反馈技术。 根据本发明的一个优选实施例，在具有1V-5V的DC输入工作范围的11晶体管电路中，在低功率子阈值中实现了具有+/- 1V线性范围的紧凑型跨导放大器 CMOS技术在标准的2微米工艺中。
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公开(公告)号：US5331215A
公开(公告)日：1994-07-19
申请号：US922535
申请日：1992-07-30
申请人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
发明人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.
摘要翻译： 根据本发明的突触阵列包括多个电适应元件。 可以通过施加产生的第一和第二电控制信号将电子放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的每个电适应元件中的浮动节点上并从其移除， 响应于适配信号。 对一行中所有突触元素的输入连接到公共行输入行。 将输入到列中的所有突触元素的调整连接到公共列适应线。 提供给列中所有放大器的电流通常由感测线提供。 为了适应本发明的M行×N列矩阵中的突触元素，要将矩阵的给定列n适应的电压放置在输入电压线上，并且列n中的突触元素 然后通过在第n列的适应线上断言适配信号同时进行调整。 用于适配连续列的输入电压的矢量可以顺序地放置在行输入电压线上，并且用于通过在适当的列适配线上断言适配信号来适应突触元件的列，直到整个阵列电气适配。 在每个突触元件已经适应之后，当突触元件的输入端的电压等于突触元件适应的电压时，流过它的电流将被最大化。 电气适应性的胜者总线电路的输入连接到阵列的列感测线。
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