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83 条记录 (耗时 0.022 秒)

    Voltage-and temperature-compensated RC oscillator circuit
    61.
    发明授权
    Voltage-and temperature-compensated RC oscillator circuit 有权
    电压和温度补偿RC振荡电路

    公开(公告)号：US07439818B2

    公开(公告)日：2008-10-21

    申请号：US11467475

    申请日：2006-08-25

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H03K3/26 ,  H03K3/02 ,  H03K3/42 ,  H03L1/00

    CPC分类号： H03K3/0231 ,  H03K3/011 ,  H03L1/022

    摘要： An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

    摘要翻译： 集成温度补偿RC振荡器电路包括具有输入和输出的反相器。 RC网络耦合在逆变器和一对比较器之间。 第一比较器具有耦合到第一参考电压的反相输入，耦合到RC网络的非反相输入和输出。 第二比较器具有耦合到RC网络的反相输入，耦合到第二参考电压的非反相输入和输出。 设置复位触发器具有耦合到第一比较器的输出的设置输入，耦合到第二比较器的输出的复位输入和耦合到反相器的输入的输出。 比较器中的差分放大器各自具有二极管连接的p沟道MOS晶体管，其控制沟道宽度小于二极管连接的p沟道电流镜晶体管的p沟道MOS晶体管。

    Integrated circuit including programmable logic and external-device chip-enable override control
    64.
    发明授权
    Integrated circuit including programmable logic and external-device chip-enable override control 有权
    集成电路，包括可编程逻辑和外部器件芯片使能覆盖控制

    公开(公告)号：US07362131B2

    公开(公告)日：2008-04-22

    申请号：US11279046

    申请日：2006-04-07

    申请人： Rabindranath Balasubramanian ,  Kurt Kolkind ,  Gregory Bakker

    发明人： Rabindranath Balasubramanian ,  Kurt Kolkind ,  Gregory Bakker

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

    摘要： An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

    摘要翻译： 集成电路装置包括可编程逻辑块，监视输入，条件感测电路，耦合到所述监控输入并且被配置为响应于感测所述监视输入处的状况而在输出处产生状态感测信号，第一数字 输入，第一数字输出和门控电路，其配置在可编程逻辑块中并耦合在第一数字输入和第一数字输出之间。 门控电路具有耦合到条件感测电路并且产生输出的选通输入。 在不存在条件感测信号的情况下，该输出与第一数字输入的输入状态相关，并且在条件感测信号存在的情况下采用超驰状态。

    Clock-generator architecture for a programmable-logic-based system on a chip
    65.
    发明授权
    Clock-generator architecture for a programmable-logic-based system on a chip 有权
    用于芯片上基于可编程逻辑的系统的时钟发生器架构

    公开(公告)号：US07298178B1

    公开(公告)日：2007-11-20

    申请号：US11427717

    申请日：2006-06-29

    申请人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

    发明人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

    IPC分类号： H03D9/00

    CPC分类号： H03K19/17732

    摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

    摘要翻译： 一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。 时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 可编程逻辑块耦合到时钟调节电路和实时时钟。

    PLD providing soft wakeup logic
    69.
    发明授权
    PLD providing soft wakeup logic 有权
    PLD提供软唤醒逻辑

    公开(公告)号：US07884640B2

    公开(公告)日：2011-02-08

    申请号：US12340358

    申请日：2008-12-19

    申请人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    发明人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17784

    摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

    摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。