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    PLD PROVIDING SOFT WAKEUP LOGIC
    1.
    发明申请
    PLD PROVIDING SOFT WAKEUP LOGIC 有权
    PLD提供软件唤醒逻辑

    公开(公告)号：US20100156457A1

    公开(公告)日：2010-06-24

    申请号：US12340358

    申请日：2008-12-19

    申请人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    发明人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    IPC分类号： H03K19/177 ,  H03K19/0175

    CPC分类号： H03K19/17784

    摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

    摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

    PLD providing soft wakeup logic
    2.
    发明授权
    PLD providing soft wakeup logic 有权
    PLD提供软唤醒逻辑

    公开(公告)号：US07884640B2

    公开(公告)日：2011-02-08

    申请号：US12340358

    申请日：2008-12-19

    申请人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    发明人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17784

    摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

    摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

    Non-volatile memory with source-side column select
    3.
    发明授权
    Non-volatile memory with source-side column select 有权
    源极列选择非易失性存储器

    公开(公告)号：US07522453B1

    公开(公告)日：2009-04-21

    申请号：US11961134

    申请日：2007-12-20

    申请人： Zhigang Wang ,  Gregory Bakker ,  Volker Hecht ,  Santosh Yachareni ,  Fethi Dhaoui ,  Vidyadhara Bellippady

    发明人： Zhigang Wang ,  Gregory Bakker ,  Volker Hecht ,  Santosh Yachareni ,  Fethi Dhaoui ,  Vidyadhara Bellippady

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416 ,  G11C16/08

    摘要： A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.

    摘要翻译： 非易失性存储器阵列段包括具有耦合到奇数源极线的漏极和耦合到偶数源极线的漏极的偶数选择晶体管的奇数选择晶体管。 两个段选择晶体管具有耦合到奇数和偶数源极线的不同源极，耦合到地的源极和耦合到段选择线的栅极的漏极。 多个奇数非易失性存储晶体管各自具有耦合到公共漏极线的漏极，耦合到奇数源极线的源极，浮动栅极和控制栅极。 多个偶数非易失性存储晶体管每个都具有耦合到公共漏极线的漏极，耦合到偶数源极线的源极，浮动栅极和控制栅极。 每个偶数非易失性存储晶体管的控制栅极耦合到奇数非易失性存储晶体管中不同一个的控制栅极。