Polyarylene ethers
    61.
    发明授权
    Polyarylene ethers 失效
    聚亚芳基醚

    公开(公告)号:US5270435A

    公开(公告)日:1993-12-14

    申请号:US816839

    申请日:1992-01-09

    摘要: Polyarylene ethers which, based on the total amount of the structural units present in the polyether resin, contain 2-100 mol % of a recurring structural unit of formula I ##STR1## and 0-98 mol % of a recurring structural unit of formula II wherein each a is 1 or 2, 10 to 100% of X, based on the total number of the bonds X present in the structural units of formulae I and II, are --SO.sub.2 --, and 0 to 90% of X are --CO--, and A is a group of formula IIIa-IIIg: ##STR2## wherein Y is --CH.sub.2 --, --C(CH.sub.3).sub.2 --, --C(CF.sub.3).sub.2 --, --S--, --SO--, --SO.sub.2 --, --O-- or --CO--, and the aromatic rings in the structural units of formulae I and II are unsubstituted or substituted by one or more alkyl groups of 1 to 4 carbon atoms, have good solubility in organic solvents and are suitable preferably for modifying other plastics materials or for use as matrix resins for the production of fibrous composite structures.

    摘要翻译: 基于存在于聚醚树脂中的结构单元的总量的聚亚芳基醚含有2-100摩尔%的式I的重复结构单元(I)和0-98摩尔%的重复结构单元 式II其中每个a为1或2,10至100%X,基于存在于式I和II的结构单元中的键X的总数为-SO 2 - ,且为 (IIIa)(IIIc)(IIIc)(IIIc)(IIId)图像(IIId)(图像)(IIId) (IIIf)(IIIg)其中Y是-CH 2 - , - C(CH 3)2 - , - C(CF 3)2 - , - S - , - SO - , - SO 2 - O-或-CO-,并且式I和II的结构单元中的芳环是未取代的或被一个或多个具有1至4个碳原子的烷基取代,在有机溶剂中具有良好的溶解度,并且适合用于改性其它 塑料材料或用作生产纤维复合结构体的基质树脂。

    Polyarylene ethers
    62.
    发明授权
    Polyarylene ethers 失效
    聚阴离子

    公开(公告)号:US5212278A

    公开(公告)日:1993-05-18

    申请号:US493058

    申请日:1990-03-13

    摘要: The invention relates to polyarylene ethers which contain, based on the total amount of structural elements present in the polyether resin, 5-100 mol % of a recurring structural element of the formula I ##STR1## and 0-95 mol % of a recurring structural element of the formula II ##STR2## in which X and X' independently of one another are --SO--, --SO.sub.2 -- or --CO--, one of the radicals R.sub.1, R.sub.2, R.sub.3 and R.sub.4 is phenyl or phenyl which is substituted by one to three (C.sub.1 -C.sub.4)alkyl groups and the remaining radicals R.sub.1, R.sub.2, R.sub.3 and R.sub.4 independently of one another are hydrogen, (C.sub.1 -C.sub.4)alkyl, phenyl or phenyl which is substituted by one to three (C.sub.1 -C.sub.4)alkyl groups, and A is an aromatic radical, at least 25% of the bonds X and/or Y and/or the bridge members contained in A being --SO.sub.2 --.These industrial materials are distinguished by very good mechanical properties and good solubility.

    摘要翻译: 本发明涉及聚亚芳基醚,它包含基于存在于聚醚树脂中的结构元素的总量,5-100mol%的式I(I)的重复结构元素和0-95mol%的 其中X和X'彼此独立地是-SO - , - SO 2 - 或-CO-的式II(II)的重复结构元件,基团R 1,R 2,R 3和R 4之一是苯基 或被一至三个(C 1 -C 4)烷基取代的苯基,其余基团R 1,R 2,R 3和R 4彼此独立地是氢,(C 1 -C 4)烷基,苯基或被一个至 三个(C 1 -C 4)烷基,A是芳族基团,A中包含的至少25%的键X和/或Y和/或桥连构成为-SO 2 - 。 这些工业材料的特征在于非常好的机械性能和良好的溶解性。

    Modified polyarylene ether sulfones

    公开(公告)号:US5212264A

    公开(公告)日:1993-05-18

    申请号:US852481

    申请日:1992-03-16

    IPC分类号: C08G75/23

    CPC分类号: C08G75/23

    摘要: There are disclosed substantially linear polyarylene ether sulfones having a reduced viscosity of having a reduced viscosity of ca. 0.25 to ca. 1.5 dl/g (measured in a 1% solution in DMF at 25.degree. C.) and consisting essentially of 95-99.8% by weight of segments of formula I and of 5-0.2% by weight of segments of formula IIa, formula IIb and/or formula IIc ##STR1## the percentages by weight being based on the entire polymer and the molecular weight (number average) of the segments of formula I being 6000 to ca. 60 000, if the polymer contains solely structural units of formula IIa and/or IIb, and 1000 to ca. 60 000 if the polymer contains more than 0.1% by weight of structural units of formula IIc, and R consists of the recurring structural units of formula Ia and/or of up to 99.8% by weight, based on the total polymer, of recurring structural units of formula Ib ##STR2## wherein R.sub.1 is C.sub.1 -C.sub.6 alkyl, C.sub.3 -C.sub.10 alkenyl, phenyl or halogen, p is an integer from 0 to 4 Ar.sub.1 and Ar.sub.2 are each independently of the other divalent carbocylic-aromatic radicals, Z.sub.1 is a divalent radical of a cycloaliphatic, aromatic or araliphatic dihydroxy compound after removal of both hydroxyl groups, Z.sub.2 is a divalent radical of a cycloaliphatic, aromatic or araliphatic di-secondary amino compound after removal of both N-hydrogen atoms, m is an integer from 1 to ca. 10, and Z.sub.3 is a trivalent radical of a cycloaliphatic, aromatic or araliphatic compound containing hydroxy and/or amino groups after removal of the hydroxyl groups and/or active hydrogen atoms bound to amino nitrogen atoms, which radicals Ar.sub.1, Ar.sub.2, Z.sub.1, Z.sub.2 and Z.sub.3 may be substituted by one to four C.sub.1 -C.sub.6 alkyl groups, C.sub.3 -C.sub.10 alkenyl groups, phenyl groups or halogen atoms, and in which radicals Z.sub.1, Z.sub.2 and Z.sub.3 one, two, three or four ring carbon atoms may be replaced by oxygen, sulfur and/or nitrogen atoms.

    Integrated semiconductor memory of the dram type and method for testing
the same
    64.
    发明授权
    Integrated semiconductor memory of the dram type and method for testing the same 失效
    集成半导体存储器的类型和测试方法

    公开(公告)号:US5184326A

    公开(公告)日:1993-02-02

    申请号:US494122

    申请日:1990-03-15

    摘要: An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

    摘要翻译: DRAM类型的集成半导体存储器包括字线和位线对。 矩阵中的存储单元连接到字线和位线。 每个位线对的一个评估器电路连接到位线。 每个位线对在操作期间被分成一个位线和一个参考位线。 提供控制线。 为每个位线提供至少一个耦合电容器,并且每个参考位线具有连接到位线对的第一引线和连接到控制线的第二引线。 用于测试DRAM类型的集成半导体存储器的方法包括从存储器单元中存储的存储单元中读取数据,在读出之前将位线对预充电到预充电电平,以及在预充电之后向每个位线对馈送附加电位。

    Soluble polyarylene ether sulfones
    65.
    发明授权
    Soluble polyarylene ether sulfones 失效
    可溶性聚亚烷基硫醚

    公开(公告)号:US5126427A

    公开(公告)日:1992-06-30

    申请号:US665492

    申请日:1991-03-06

    CPC分类号: C08G75/23 C08L63/00

    摘要: Polyarylene ether sulfones which have a reduced viscosity of 0.1 to 2.0 dl/g, measured at 25.degree. C. in a 1% solution in N-methylpyrrolidone (NMP), and which contain, based on the total number of structural units present in the polyarylene ether sulfone resin, 99-1 mol % of a recurring structural unit of formula I ##STR1## and 1-99 mol % of a recurring structural unit of formula II--O--Ar.sub.2 --O--Ar.sub.1 -- (II)wherein the aromatic rings in the structural unit of formula I are unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, Ar.sub.1 is a radical of formula IIIa-IIIc ##STR2## wherein a is 0 or 1, ##STR3## which radical is unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, and Ar.sub.2 is a radical of formula IVa-IVe ##STR4## wherein b is 0 or 1 ##STR5## wherein c is 0 or 1 ##STR6## wherein Z is --CO--, --SO.sub.2 --, --SO--, --S--, --O--, ##STR7## wherein R is methyl or phenyl, which radical is unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, are soluble in customary organic solvents and can be processed from the solution to films or incorporated in other matrix resins.

    摘要翻译: 在25℃下在1%N-甲基吡咯烷酮(NMP)溶液中测定的具有0.1至2.0dl / g的比浓粘度的聚亚芳基醚砜,并且基于存在于 聚亚芳基醚砜树脂,99-1摩尔%的式I的重复结构单元(I)和1-99mol%的式II-O-Ar-O-Ar1-(II)的重复结构单元, 其中式I的结构单元中的芳环是未取代的或被一个或多个C 1 -C 4烷基,C 1 -C 4烷氧基或卤素原子取代,Ar 1是式IIIa-IIIc(IIIa)的基团,其中a是 0或1,(IIIb)或(IIIc),该基团是未取代的或被一个或多个C 1 -C 4烷基,C 1 -C 4烷氧基或卤素原子取代,Ar 2是式IVa-IVe基团 (IVa)其中b为0或1(IVb)(IVc)(IVc)其中c为0或1(IVe)其中Z为-CO-, - SO2-,-SO-,-S-,-O-, 其中R是甲基或苯基,该基团是未被取代的或被一个或多个C 1 -C 4烷基,C 1 -C 4烷氧基或卤原子取代的,可溶于常规有机溶剂中,并且可以从溶液中加工成膜或并入 其他基体树脂。

    Integrated semiconductor memory
    67.
    发明授权
    Integrated semiconductor memory 失效
    集成半导体存储器

    公开(公告)号:US4742489A

    公开(公告)日:1988-05-03

    申请号:US811886

    申请日:1985-12-20

    申请人: Kurt Hoffmann

    发明人: Kurt Hoffmann

    CPC分类号: G11C29/26

    摘要: An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data. It further has evaluation circuits connected to n of the n.multidot.m data lines parallel to the respective second data separators. It also has third data separators connected between each of the m data input terminals and the n of n.multidot.m data lines parallel to the first data separators for transferring the memory data in parallel to all of the n data lines in response to the control signal, and fourth data separators each preceding a respective one of the m data output terminals for selectively feeding the memory data selected by the second data separators or the output signal generated by the evaluation circuit to the data output terminals in response to the control signal and a complementary signal.

    摘要翻译: 集成半导体存储器包括n个相同的存储单元场,每个存储单元场均具有数据宽度等于m,n×m个数据线,用于将存储器数据写入和读出存储单元区域; m个第一数据分离器,用于施加存储器数据 作为在写入时寻址数据的功能,m个第二数据分离器用于响应于寻址数据选择n条数据线之一。 它还具有连接到平行于各个第二数据分离器的n×m数据线中的n个的评估电路。 它还具有连接在每个m个数据输入端之间的第三数据分离器和与第一数据分离器并联的n×m个数据线的n个,用于响应于控制信号并行传送存储数据到所有n条数据线;以及 第四数据分离器,每个在m个数据输出端子中的相应一个之前,用于响应于控制信号和互补信号选择性地将由第二数据分离器选择的存储器数据或由评估电路产生的输出信号馈送到数据输出端子 。

    Monolithically integrated semiconductor circuit with transistors
    68.
    发明授权
    Monolithically integrated semiconductor circuit with transistors 失效
    具有晶体管的单片集成半导体电路

    公开(公告)号:US4549096A

    公开(公告)日:1985-10-22

    申请号:US533615

    申请日:1983-09-19

    申请人: Kurt Hoffmann

    发明人: Kurt Hoffmann

    CPC分类号: G05F3/205 H01L27/0222

    摘要: Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circuit proper is produced.

    摘要翻译: 具有晶体管的半导体集成半导体电路,其半导体电路本体具有形成在半导体芯片的前侧上的元件,半导体芯片的表面还具有可由相应电源供应的两个电源端子,一方面, 另一方面涉及用于产生施加到占据半导体芯片背面的衬底区域的衬底偏置的附加电路部分,并且分别连接到属于该半导体电路的至少一个半导体区域的附加电路部分 半导体电路本体和半导体芯片的前侧上的栅极电极,其控制半导体区域并与其绝缘,包括基板偏置发生器和正确划分两个电源端子处的电压的半导体电路的串联连接 以使得所需的参考电位成为半导体芯片的方式 r生产半导体电路。

    Monolithically integrated semiconductor memory
    69.
    发明授权
    Monolithically integrated semiconductor memory 失效
    单片集成半导体存储器

    公开(公告)号:US4441171A

    公开(公告)日:1984-04-03

    申请号:US339156

    申请日:1982-01-13

    申请人: Kurt Hoffmann

    发明人: Kurt Hoffmann

    CPC分类号: G11C11/4091

    摘要: Monolithically integrated semiconductor memory, including a matrix of identical memory cells disposed in a set of row members and a set of column members, each of the memory cells including a single MOS-field effect transistor and a storage capacitor, a comparator, and a comparison cell, the comparison cell being in the form of a memory cell including a single MOS-field effect transistor and a storage capacitor, the comparator and the comparison cell being assigned to each of the members of one of the sets, each of the comparators within the matrix of single-transistor memory cells including a flip-flop memory cell constructed in complimentary MOS-technology.

    摘要翻译: 单片集成半导体存储器,包括设置在一组行成员中的相同存储器单元的矩阵和一组列构件,每个存储单元包括单个MOS场效应晶体管和存储电容器,比较器和比较 单元,比较单元是包括单个MOS场效应晶体管和存储电容器的存储单元的形式,比较器和比较单元被分配给每个组中的每一个,每个比较器内部 包括以补偿MOS技术构成的触发器存储单元的单晶体管存储单元的矩阵。

    One-transistor dynamic ram with poly bit lines
    70.
    发明授权
    One-transistor dynamic ram with poly bit lines 失效
    具有多位线的单晶体管动态RAM

    公开(公告)号:US4334236A

    公开(公告)日:1982-06-08

    申请号:US67926

    申请日:1979-08-20

    摘要: An MOS integrated semiconductor memory is disclosed with memory locations arranged in lines and columns. The memory locations in each case contain two one-transistor memory cells. For each memory location, two MOS transistors of the two one-transistor memory cells are controlled in common by means of a word line which runs in a line direction. The two MOS transistors are each coupled on a respective bit line which runs on one side of the memory locations in a column direction. Electrodes of the MOS memory capacitors and the gates of the MOS transistors of the one-transistor memory cells are formed by a first polysilicon layer and a second polysilicon layer, respectively. For reduction of area and also of bit line capacitance as well as at the same time raising the memory capacitance, the invention provides that the bit lines are provided as a third polysilicon layer forming polysilicon paths, and that the polysilicon paths which form the bit lines are coupled on only via limited doped connection zones in a semiconductor substrate which contains the memory cells of the MOS transistors.

    摘要翻译: 公开了一种MOS集成半导体存储器,其具有以行和列布置的存储器位置。 每种情况下的存储器位置都包含两个单晶体管存储单元。 对于每个存储器位置,两个单晶体管存储单元的两个MOS晶体管通过在线方向上运行的字线被共同控制。 两个MOS晶体管分别耦合在沿列方向在存储单元的一侧上运行的相应位线上。 MOS存储电容器的电极和单晶体管存储单元的MOS晶体管的栅极分别由第一多晶硅层和第二多晶硅层形成。 为了减小面积和位线电容以及同时提高存储电容,本发明提供了将位线设置为形成多晶硅路径的第三多晶硅层,并且形成位线的多晶硅路径 仅通过包含MOS晶体管的存储单元的半导体衬底中的有限掺杂连接区域耦合。