摘要:
Polyarylene ethers which, based on the total amount of the structural units present in the polyether resin, contain 2-100 mol % of a recurring structural unit of formula I ##STR1## and 0-98 mol % of a recurring structural unit of formula II wherein each a is 1 or 2, 10 to 100% of X, based on the total number of the bonds X present in the structural units of formulae I and II, are --SO.sub.2 --, and 0 to 90% of X are --CO--, and A is a group of formula IIIa-IIIg: ##STR2## wherein Y is --CH.sub.2 --, --C(CH.sub.3).sub.2 --, --C(CF.sub.3).sub.2 --, --S--, --SO--, --SO.sub.2 --, --O-- or --CO--, and the aromatic rings in the structural units of formulae I and II are unsubstituted or substituted by one or more alkyl groups of 1 to 4 carbon atoms, have good solubility in organic solvents and are suitable preferably for modifying other plastics materials or for use as matrix resins for the production of fibrous composite structures.
摘要:
The invention relates to polyarylene ethers which contain, based on the total amount of structural elements present in the polyether resin, 5-100 mol % of a recurring structural element of the formula I ##STR1## and 0-95 mol % of a recurring structural element of the formula II ##STR2## in which X and X' independently of one another are --SO--, --SO.sub.2 -- or --CO--, one of the radicals R.sub.1, R.sub.2, R.sub.3 and R.sub.4 is phenyl or phenyl which is substituted by one to three (C.sub.1 -C.sub.4)alkyl groups and the remaining radicals R.sub.1, R.sub.2, R.sub.3 and R.sub.4 independently of one another are hydrogen, (C.sub.1 -C.sub.4)alkyl, phenyl or phenyl which is substituted by one to three (C.sub.1 -C.sub.4)alkyl groups, and A is an aromatic radical, at least 25% of the bonds X and/or Y and/or the bridge members contained in A being --SO.sub.2 --.These industrial materials are distinguished by very good mechanical properties and good solubility.
摘要:
There are disclosed substantially linear polyarylene ether sulfones having a reduced viscosity of having a reduced viscosity of ca. 0.25 to ca. 1.5 dl/g (measured in a 1% solution in DMF at 25.degree. C.) and consisting essentially of 95-99.8% by weight of segments of formula I and of 5-0.2% by weight of segments of formula IIa, formula IIb and/or formula IIc ##STR1## the percentages by weight being based on the entire polymer and the molecular weight (number average) of the segments of formula I being 6000 to ca. 60 000, if the polymer contains solely structural units of formula IIa and/or IIb, and 1000 to ca. 60 000 if the polymer contains more than 0.1% by weight of structural units of formula IIc, and R consists of the recurring structural units of formula Ia and/or of up to 99.8% by weight, based on the total polymer, of recurring structural units of formula Ib ##STR2## wherein R.sub.1 is C.sub.1 -C.sub.6 alkyl, C.sub.3 -C.sub.10 alkenyl, phenyl or halogen, p is an integer from 0 to 4 Ar.sub.1 and Ar.sub.2 are each independently of the other divalent carbocylic-aromatic radicals, Z.sub.1 is a divalent radical of a cycloaliphatic, aromatic or araliphatic dihydroxy compound after removal of both hydroxyl groups, Z.sub.2 is a divalent radical of a cycloaliphatic, aromatic or araliphatic di-secondary amino compound after removal of both N-hydrogen atoms, m is an integer from 1 to ca. 10, and Z.sub.3 is a trivalent radical of a cycloaliphatic, aromatic or araliphatic compound containing hydroxy and/or amino groups after removal of the hydroxyl groups and/or active hydrogen atoms bound to amino nitrogen atoms, which radicals Ar.sub.1, Ar.sub.2, Z.sub.1, Z.sub.2 and Z.sub.3 may be substituted by one to four C.sub.1 -C.sub.6 alkyl groups, C.sub.3 -C.sub.10 alkenyl groups, phenyl groups or halogen atoms, and in which radicals Z.sub.1, Z.sub.2 and Z.sub.3 one, two, three or four ring carbon atoms may be replaced by oxygen, sulfur and/or nitrogen atoms.
摘要:
An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.
摘要:
Polyarylene ether sulfones which have a reduced viscosity of 0.1 to 2.0 dl/g, measured at 25.degree. C. in a 1% solution in N-methylpyrrolidone (NMP), and which contain, based on the total number of structural units present in the polyarylene ether sulfone resin, 99-1 mol % of a recurring structural unit of formula I ##STR1## and 1-99 mol % of a recurring structural unit of formula II--O--Ar.sub.2 --O--Ar.sub.1 -- (II)wherein the aromatic rings in the structural unit of formula I are unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, Ar.sub.1 is a radical of formula IIIa-IIIc ##STR2## wherein a is 0 or 1, ##STR3## which radical is unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, and Ar.sub.2 is a radical of formula IVa-IVe ##STR4## wherein b is 0 or 1 ##STR5## wherein c is 0 or 1 ##STR6## wherein Z is --CO--, --SO.sub.2 --, --SO--, --S--, --O--, ##STR7## wherein R is methyl or phenyl, which radical is unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, are soluble in customary organic solvents and can be processed from the solution to films or incorporated in other matrix resins.
摘要:
A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.
摘要:
An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data. It further has evaluation circuits connected to n of the n.multidot.m data lines parallel to the respective second data separators. It also has third data separators connected between each of the m data input terminals and the n of n.multidot.m data lines parallel to the first data separators for transferring the memory data in parallel to all of the n data lines in response to the control signal, and fourth data separators each preceding a respective one of the m data output terminals for selectively feeding the memory data selected by the second data separators or the output signal generated by the evaluation circuit to the data output terminals in response to the control signal and a complementary signal.
摘要:
Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circuit proper is produced.
摘要:
Monolithically integrated semiconductor memory, including a matrix of identical memory cells disposed in a set of row members and a set of column members, each of the memory cells including a single MOS-field effect transistor and a storage capacitor, a comparator, and a comparison cell, the comparison cell being in the form of a memory cell including a single MOS-field effect transistor and a storage capacitor, the comparator and the comparison cell being assigned to each of the members of one of the sets, each of the comparators within the matrix of single-transistor memory cells including a flip-flop memory cell constructed in complimentary MOS-technology.
摘要:
An MOS integrated semiconductor memory is disclosed with memory locations arranged in lines and columns. The memory locations in each case contain two one-transistor memory cells. For each memory location, two MOS transistors of the two one-transistor memory cells are controlled in common by means of a word line which runs in a line direction. The two MOS transistors are each coupled on a respective bit line which runs on one side of the memory locations in a column direction. Electrodes of the MOS memory capacitors and the gates of the MOS transistors of the one-transistor memory cells are formed by a first polysilicon layer and a second polysilicon layer, respectively. For reduction of area and also of bit line capacitance as well as at the same time raising the memory capacitance, the invention provides that the bit lines are provided as a third polysilicon layer forming polysilicon paths, and that the polysilicon paths which form the bit lines are coupled on only via limited doped connection zones in a semiconductor substrate which contains the memory cells of the MOS transistors.