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    Reducing programming disturbance in memory devices
    61.
    发明授权
    Reducing programming disturbance in memory devices 有权

    公开(公告)号：US11688470B2

    公开(公告)日：2023-06-27

    申请号：US17751131

    申请日：2022-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.

    Memory block select circuitry including voltage bootstrapping control
    63.
    发明授权
    Memory block select circuitry including voltage bootstrapping control 有权

    公开(公告)号：US11302397B2

    公开(公告)日：2022-04-12

    申请号：US16995361

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/10 ,  H01L27/11529 ,  H01L27/11573 ,  G11C11/56 ,  G11C16/04

    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

    MEMORY DEVICE INCLUDING DATA LINES ON MULTIPLE DEVICE LEVELS
    64.
    发明申请
    MEMORY DEVICE INCLUDING DATA LINES ON MULTIPLE DEVICE LEVELS 有权

    公开(公告)号：US20210193570A1

    公开(公告)日：2021-06-24

    申请号：US16723758

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Paolo Tessariol ,  Aaron Yip ,  Naveen Kaushik

    IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/768

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

    Memories having select devices between access lines and in memory cells
    65.
    发明授权
    Memories having select devices between access lines and in memory cells 有权

    公开(公告)号：US10418072B2

    公开(公告)日：2019-09-17

    申请号：US16188957

    申请日：2018-11-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron Yip

    IPC: G11C5/06 ,  G11C13/00 ,  G11C7/18

    Abstract: Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells comprises a respective second bi-directional select device, of a plurality of second bi-directional select devices, and a respective programmable element, of a plurality of programmable elements, connected in series.

    3D memory device including shared select gate connections between memory blocks
    66.
    发明授权
    3D memory device including shared select gate connections between memory blocks 有权

    公开(公告)号：US10170188B1

    公开(公告)日：2019-01-01

    申请号：US15693118

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08

    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

    METHODS AND DEVICES FOR MEMORY READS WITH PRECHARGED DATA LINES
    70.
    发明申请
    METHODS AND DEVICES FOR MEMORY READS WITH PRECHARGED DATA LINES 有权
    使用预置数据线的存储器读取的方法和设备

    公开(公告)号：US20140029353A1

    公开(公告)日：2014-01-30

    申请号：US14039796

    申请日：2013-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/24

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.

    Abstract translation: 操作存储器件的方法，包括将相邻数据线对预充电到特定电压，将相邻数据线对的一条数据线与特定电压隔离，同时将相邻数据线对的另一条数据线保持在特定电压 并且根据与该一条数据线相关联的一组存储单元的所选存储单元的数据值选择性地放电一条数据线。

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