公开(公告)号：US20200051613A1

公开(公告)日：2020-02-13

申请号：US16404525

申请日：2019-05-06

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4097

Abstract: Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.

公开(公告)号：US10535388B1

公开(公告)日：2020-01-14

申请号：US16038063

申请日：2018-07-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles L. Ingalls

IPC: G11C7/06 ,  G11C8/18 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

公开(公告)号：US20190333564A1

公开(公告)日：2019-10-31

申请号：US16417004

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US10431291B1

公开(公告)日：2019-10-01

申请号：US16058600

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US20190206480A1

公开(公告)日：2019-07-04

申请号：US15857327

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108

CPC classification number: G11C11/4091 ,  H01L27/10897

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US20180350420A1

公开(公告)日：2018-12-06

申请号：US16035135

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US10115438B2

公开(公告)日：2018-10-30

申请号：US15667234

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06 ,  G11C7/22

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US20170365318A1

公开(公告)日：2017-12-21

申请号：US15641020

申请日：2017-07-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20140226427A1

公开(公告)日：2014-08-14

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个局部字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20240306399A1

公开(公告)日：2024-09-12

申请号：US18666498

申请日：2024-05-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H10B53/30 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H10B12/00 ,  H10B53/20

CPC classification number: H10B53/30 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/78 ,  H01L29/7827 ,  H10B12/00 ,  H10B53/20 ,  H01L27/0207 ,  H01L28/75

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.