公开(公告)号：US20230245701A1

公开(公告)日：2023-08-03

申请号：US17588718

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Andrea Ghetti ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/003 ,  G11C13/0004 ,  G11C2213/30 ,  G11C2213/15

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.

公开(公告)号：US11670368B2

公开(公告)日：2023-06-06

申请号：US17512586

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0045

Abstract: A method for reading memory cells is described. The method may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US20230110946A1

公开(公告)日：2023-04-13

申请号：US17044150

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

IPC: G06F3/06

Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

公开(公告)号：US11626151B2

公开(公告)日：2023-04-11

申请号：US16983469

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20230067396A1

公开(公告)日：2023-03-02

申请号：US17463152

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Yen Chun Lee ,  Ferdinando Bedeschi

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C7/10

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.

公开(公告)号：US11594297B2

公开(公告)日：2023-02-28

申请号：US17590532

申请日：2022-02-01

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12

Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

公开(公告)号：US11587604B2

公开(公告)日：2023-02-21

申请号：US17241889

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

公开(公告)号：US11545219B2

公开(公告)日：2023-01-03

申请号：US16975619

申请日：2020-03-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C7/00 ,  G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

公开(公告)号：US20220392527A1

公开(公告)日：2022-12-08

申请号：US17880804

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00 ,  H01L45/00

Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

公开(公告)号：US20220122659A1

公开(公告)日：2022-04-21

申请号：US17512586

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure relates to a method for reading memory cells, and may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.