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    Memory system and method using ECC with flag bit to identify modified data
    61.
    发明授权
    Memory system and method using ECC with flag bit to identify modified data 有权

    公开(公告)号：US08601341B2

    公开(公告)日：2013-12-03

    申请号：US13855534

    申请日：2013-04-02

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski ,  John F. Schreck

    IPC: H03M13/00

    CPC classification number: H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

    Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

    MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA
    62.
    发明申请
    MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA 有权
    使用部分ECC来实现低功率刷新和快速访问数据的存储器系统和方法

    公开(公告)号：US20130139029A1

    公开(公告)日：2013-05-30

    申请号：US13746504

    申请日：2013-01-22

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

    Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

    Abstract translation: DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

    MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY
    64.
    发明申请
    MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY 有权

    公开(公告)号：US20220350760A1

    公开(公告)日：2022-11-03

    申请号：US17864629

    申请日：2022-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

    IPC: G06F13/16 ,  G06F12/0813 ,  G06F15/78 ,  G06F3/06 ,  G06F9/30 ,  G06F13/40

    Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

    APPARATUSES AND METHODS FOR MEMORY ADDRESS TRANSLATION DURING BLOCK MIGRATION
    66.
    发明申请
    APPARATUSES AND METHODS FOR MEMORY ADDRESS TRANSLATION DURING BLOCK MIGRATION 有权

    公开(公告)号：US20210042219A1

    公开(公告)日：2021-02-11

    申请号：US17079138

    申请日：2020-10-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

    IPC: G06F12/02 ,  G06F13/16

    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

    Progressive length error control code
    68.
    发明授权
    Progressive length error control code 有权

    公开(公告)号：US10409680B1

    公开(公告)日：2019-09-10

    申请号：US15988962

    申请日：2018-05-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： J. Thomas Pawlowski

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

    Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

    MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY
    70.
    发明申请
    MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY 审中-公开
    具有内部处理器的内存和内存中的数据通信方法

    公开(公告)号：US20170024337A1

    公开(公告)日：2017-01-26

    申请号：US15288077

    申请日：2016-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

    IPC: G06F13/16 ,  G06F13/40 ,  G06F9/30 ,  G06F3/06

    CPC classification number: G06F13/1673 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30043 ,  G06F12/0813 ,  G06F13/4068 ,  G06F15/7821

    Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

    Abstract translation: 提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。 在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。 内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。 此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。 因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

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