公开(公告)号：US11556267B2

公开(公告)日：2023-01-17

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

公开(公告)号：US11532348B2

公开(公告)日：2022-12-20

申请号：US17110128

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jeremy Wayne Butterfield ,  Jeremy Binfet

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C5/14 ,  G11C5/06 ,  G11C11/409

Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.

公开(公告)号：US11487436B2

公开(公告)日：2022-11-01

申请号：US16995083

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, Jr. ,  Niccolo' Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06 ,  G06F11/34 ,  G06F11/30

Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.

公开(公告)号：US11423976B2

公开(公告)日：2022-08-23

申请号：US16896750

申请日：2020-06-09

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C16/20 ,  G11C16/26 ,  G11C7/20 ,  G11C16/04

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US11309052B2

公开(公告)日：2022-04-19

申请号：US17001723

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/42 ,  G11C29/44 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20220068426A1

公开(公告)日：2022-03-03

申请号：US17001723

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/12 ,  G06F11/07 ,  G06F11/30

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20220066642A1

公开(公告)日：2022-03-03

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

公开(公告)号：US10453538B2

公开(公告)日：2019-10-22

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/115

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US08767467B2

公开(公告)日：2014-07-01

申请号：US13970055

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Krishna K. Parat ,  Akira Goda ,  Koichi Kawal ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC: G11C16/04

CPC classification number: G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。