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    Memory device and method of operation
    61.
    发明授权
    Memory device and method of operation 有权

    公开(公告)号：US11581043B2

    公开(公告)日：2023-02-14

    申请号：US17477854

    申请日：2021-09-17

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/08 ,  G11C16/30 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/32 ,  G11C11/56

    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

    Memory device and method of operation
    62.
    发明授权
    Memory device and method of operation 有权

    公开(公告)号：US11127463B2

    公开(公告)日：2021-09-21

    申请号：US17166879

    申请日：2021-02-03

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/08 ,  G11C16/30 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/32

    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

    Comparator
    63.
    发明授权
    Comparator 有权

    公开(公告)号：US11125819B2

    公开(公告)日：2021-09-21

    申请号：US16795769

    申请日：2020-02-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shigekazu Yamada

    IPC: G01R31/3177 ,  G01R31/317 ,  G11C29/38

    Abstract: A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.

    MONITORING AND CHARGING INHIBIT BIT-LINE
    66.
    发明申请
    MONITORING AND CHARGING INHIBIT BIT-LINE 审中-公开

    公开(公告)号：US20200118634A1

    公开(公告)日：2020-04-16

    申请号：US16716043

    申请日：2019-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/24 ,  G11C16/10 ,  G11C16/30 ,  G11C16/04

    Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.

    Controlling discharge of a control gate voltage
    67.
    发明授权
    Controlling discharge of a control gate voltage 有权

    公开(公告)号：US10347320B1

    公开(公告)日：2019-07-09

    申请号：US15866982

    申请日：2018-01-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shigekazu Yamada

    IPC: G11C16/14 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/16 ,  G11C11/4094 ,  G11C7/22 ,  G11C7/12 ,  G11C7/08 ,  G11C7/18 ,  G11C7/10 ,  G11C16/24

    Abstract: Methods of operating a memory include concurrently discharging a voltage level of a data line and source of the memory, monitoring a representation of a voltage difference between a voltage level of a control gate of a transistor connected between the data line and the source and a voltage level of the data line, activating a current path between the control gate of the transistor and the source if the voltage difference is deemed to be greater than a first value, and deactivating the current path if the voltage difference is deemed to be less than a second value. Memory configured to perform such methods include comparators configured to monitor voltage nodes capacitively coupled to the data line and to the control gate of the transistor connected between the data line and the source, and a current path selectively connecting the control gate of the transistor to the source.

    Semiconductor memory column decoder device and method
    68.
    发明授权
    Semiconductor memory column decoder device and method 有权

    公开(公告)号：US10056149B2

    公开(公告)日：2018-08-21

    申请号：US15259957

    申请日：2016-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada ,  Tomoharu Tanaka

    IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

    Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

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