公开(公告)号：US10153022B1

公开(公告)日：2018-12-11

申请号：US15619163

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US20180294025A1

公开(公告)日：2018-10-11

申请号：US15951006

申请日：2018-04-11

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

公开(公告)号：US10032496B1

公开(公告)日：2018-07-24

申请号：US15662218

申请日：2017-07-27

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/14 ,  G11C11/22 ,  G11C11/24

Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

公开(公告)号：US20160180933A1

公开(公告)日：2016-06-23

申请号：US15054984

申请日：2016-02-26

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Simone Lombardo

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C2211/5645 ,  G11C2213/72

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

Abstract translation: 装置和方法利用复制电路来产生用于对诸如相变存储器（PCM）的存储单元的存储器单元进行编程的电压。 通过包括要编程的存储器单元的电路的电流以缩放或非缩放的方式被镜像，并被提供给复制电路的输入。 复制电路表示编程存储单元时应该遇到的电压降。 还向复制电路提供输入电压，其影响复制电路内表示电池电压降的电压降。 然后可以将复制电路上的电压降镜像并提供给偏置包括存储器单元的电路。

公开(公告)号：US20140321201A1

公开(公告)日：2014-10-30

申请号：US14325075

申请日：2014-07-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Di Vincenzo ,  Carlo Lisi

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/009

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract translation: 本文公开的主题涉及存储器件，更具体地，涉及对存储器单元的编程。

公开(公告)号：US20140285240A1

公开(公告)日：2014-09-25

申请号：US14299693

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Marco Sforzin

IPC: H03K19/0185

CPC classification number: H03K19/018528 ,  H03K19/00

Abstract: Buffers, integrated circuits, apparatuses, and methods for adjusting drive strength of a buffer are disclosed. In an example apparatus, the buffer includes a driver. The driver includes a pull-up circuit coupled to a supply voltage node and an output node, and also includes a pull-down circuit coupled to a reference voltage node and the output node. A drive adjust circuit is coupled to at least one of the pull-up circuit and the pull-down circuit, with the drive adjust circuit configured to receive a feedback signal and, based at least in part on the feedback signal, adjust a current conducted through the at least one of the pull-up and pull-down circuits.

Abstract translation: 公开了用于调节缓冲器的驱动强度的缓冲器，集成电路，装置和方法。 在示例性装置中，缓冲器包括驱动器。 驱动器包括耦合到电源电压节点和输出节点的上拉电路，并且还包括耦合到参考电压节点和输出节点的下拉电路。 驱动调节电路被耦合到上拉电路和下拉电路中的至少一个，驱动调整电路被配置为接收反馈信号，并且至少部分地基于反馈信号调整传导的电流 通过上拉和下拉电路中的至少一个。

公开(公告)号：US12183380B2

公开(公告)日：2024-12-31

申请号：US17362348

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C7/06 ,  G11C7/14 ,  G11C11/22 ,  G11C11/24

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US11942151B2

公开(公告)日：2024-03-26

申请号：US17720957

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

公开(公告)号：US11869565B2

公开(公告)日：2024-01-09

申请号：US18056516

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G06F11/07

CPC classification number: G11C11/2273 ,  G06F11/0727 ,  G06F11/0751 ,  G11C11/221 ,  G11C11/2259

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US11842783B2

公开(公告)日：2023-12-12

申请号：US16976690

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/00 ,  G11C29/46 ,  G11C29/12 ,  G11C29/42

CPC classification number: G11C29/46 ,  G11C29/1201 ,  G11C29/42

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:



storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.