公开(公告)号：US20200328223A1

公开(公告)日：2020-10-15

申请号：US16384421

申请日：2019-04-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768 ,  H01L21/764 ,  H01L29/06

Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

公开(公告)号：US20190181339A1

公开(公告)日：2019-06-13

申请号：US15836446

申请日：2017-12-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Dai-Ying Lee ,  FENG-MIN LEE

IPC: H01L45/00 ,  H01L21/8229 ,  H01L27/24 ,  G11C11/16

Abstract: Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.

公开(公告)号：US20190139885A1

公开(公告)日：2019-05-09

申请号：US15806551

申请日：2017-11-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L23/528 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L23/528 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11568 ,  H01L27/11582

Abstract: A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.

公开(公告)号：US20190088643A1

公开(公告)日：2019-03-21

申请号：US16183847

申请日：2018-11-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang ,  Dai-Ying Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11556 ,  H01L21/265 ,  H01L21/266 ,  H01L27/11524 ,  H01L21/28

CPC classification number: H01L27/0688 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28167 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

公开(公告)号：US20180337191A1

公开(公告)日：2018-11-22

申请号：US15595974

申请日：2017-05-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L29/4234

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

公开(公告)号：US10043819B1

公开(公告)日：2018-08-07

申请号：US15597965

申请日：2017-05-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/11 ,  H01L23/52 ,  H01L21/82 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11524 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04

Abstract: A 3D memory device includes a plurality of vertical pillars composed of a vertical channel and a multilayer data storage structure. The multilayer data storage structure can comprise a dielectric charge trapping structure. A stack of dielectric lined conductive strips separated in the stack by insulating strips have sidewalls disposed adjacent the corresponding vertical pillars. The conductive strips have a dielectric liner having a dielectric constant κ greater than 7 on the sidewalls in contact with the outside layer of the multilayer data storage structure on the corresponding pillar. The conductive strips in embodiments described herein can comprise a relatively low resistance material, such as a metal or a metal nitride. A manufacturing method using Si—Ge selective etching of sacrificial layers can be used in a gate replacement process to form the dielectric conductive strips.

公开(公告)号：US20170186755A1

公开(公告)日：2017-06-29

申请号：US14979863

申请日：2015-12-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L21/033 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

公开(公告)号：US09559113B2

公开(公告)日：2017-01-31

申请号：US14267493

申请日：2014-05-01

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.

Abstract translation: 存储器件包括存储器单元串的阵列。 该装置包括由绝缘材料隔开的多个导体条叠层，包括导电条的至少底面，导电条的多个中间平面和导电条的顶面。 多个垂直活动条形成在多个堆叠之间。 电荷存储结构形成在多个中间平面中的导电带的侧表面之间的交界处的接口区域中，以及多个垂直活动带中的垂直活动带。 具有与电荷存储结构不同的组成的栅极电介质形成在导电条的顶部平面中的至少一个中的导电条的垂直有源条和侧表面之间的交叉点的界面区域中，并且 导电条。

公开(公告)号：US09484353B1

公开(公告)日：2016-11-01

申请号：US14803218

申请日：2015-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Wei-Chen Chen ,  Dai-Ying Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/28273 ,  H01L29/04 ,  H01L29/16 ,  H01L29/7889

Abstract: A memory device includes a first insulating layer, a second insulating layer, an isolation layer, a floating gate electrode, a control gate electrode, a channel layer and a tunneling oxide layer. The second insulating layer is disposed adjacent to and substantially parallel with the first insulating layer to form an interlayer space there between. The isolation layer is disposed in the interlayer space to form a non-straight angle with the first insulating layer, and divides the interlayer space into a first recess and a second recess. The floating gate electrode is disposed in the first recess. The control gate electrode is disposed in the second recess. The channel layer is disposed on an opening surface of the first recess and forms a non-straight angle with the first insulating layer. The tunneling oxide layer is disposed between the channel layer and the floating gate electrode.

Abstract translation: 存储器件包括第一绝缘层，第二绝缘层，隔离层，浮栅电极，控制栅电极，沟道层和隧道氧化物层。 第二绝缘层设置成与第一绝缘层相邻并基本上平行，以在其之间形成层间空间。 隔离层设置在层间空间中以与第一绝缘层形成非直角，并且将层间空间划分成第一凹部和第二凹部。 浮栅电极设置在第一凹槽中。 控制栅电极设置在第二凹槽中。 沟道层设置在第一凹部的开口表面上并与第一绝缘层形成非直角。 隧道氧化物层设置在沟道层和浮栅之间。

公开(公告)号：US09425391B1

公开(公告)日：2016-08-23

申请号：US14638189

申请日：2015-03-04

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract translation: 提供了一种用于制造存储器的方法。 在层间导体阵列之上形成绝缘层，并蚀刻以形成对应于阵列中的第一层间导体的第一开口，其中蚀刻停止在第一层间导体的第一顶表面处。 金属氧化物层形成在第一顶表面上。 第一层阻挡材料与第一开口的金属氧化物层和表面共形并与其接触。 随后，绝缘层被蚀刻以限定对应于阵列中的第二层间导体的第二开口，其中蚀刻停止在第二层间导体的第二顶表面处。 第二层阻挡材料与第一开口中的第一阻隔材料层共形并与其接触。 第一个开口填充有导电材料。