公开(公告)号：US08354720B2

公开(公告)日：2013-01-15

申请号：US13529558

申请日：2012-06-21

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L27/12

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

公开(公告)号：US20120306026A1

公开(公告)日：2012-12-06

申请号：US13118750

申请日：2011-05-31

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field.

摘要翻译： 在替代栅极结构中采用钨阻挡部分以阻止材料从金属部分扩散到功函件材料部分。 钨阻挡部分有效地用作金属部分和功函材料部分之间的扩散阻挡层，使得功函数材料部分的组成不受包括替换栅极结构的场效应晶体管的退火和/或使用的影响。 因此，场效应晶体管的阈值电压可以在整个处理步骤和现场使用中保持稳定。

公开(公告)号：US20120292602A1

公开(公告)日：2012-11-22

申请号：US13111615

申请日：2011-05-19

申请人： DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L51/10 ,  H01L51/40

CPC分类号： H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

摘要： A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

摘要翻译： 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US08138547B2

公开(公告)日：2012-03-20

申请号：US12548005

申请日：2009-08-26

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78624

摘要： A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

摘要翻译： 公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。 在半导体层中形成源延伸和漏扩展区。 在半导体层中形成深漏极区域和深源极区域。 第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触 并且栅极屏蔽金属沉积物抵靠深漏极区域。 在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

公开(公告)号：US20120043585A1

公开(公告)日：2012-02-23

申请号：US12860977

申请日：2010-08-23

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L29/772

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

公开(公告)号：US20120007183A1

公开(公告)日：2012-01-12

申请号：US12832829

申请日：2010-07-08

申请人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

发明人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

摘要翻译： 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

公开(公告)号：US20110121370A1

公开(公告)日：2011-05-26

申请号：US12625827

申请日：2009-11-25

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

摘要翻译： 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极叠层相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US09076873B2

公开(公告)日：2015-07-07

申请号：US12986342

申请日：2011-01-07

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L29/49

CPC分类号： H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

公开(公告)号：US08890116B2

公开(公告)日：2014-11-18

申请号：US13610089

申请日：2012-09-11

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/06 ,  H01L51/00 ,  B82Y10/00 ,  H01L51/05

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

摘要翻译： 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US08785911B2

公开(公告)日：2014-07-22

申请号：US13167570

申请日：2011-06-23

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

IPC分类号： H01L21/336

CPC分类号： H01L29/7781 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1075 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055

摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

摘要翻译： 提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。