公开(公告)号：US20090287390A1

公开(公告)日：2009-11-19

申请号：US12465194

申请日：2009-05-13

申请人： Hiroyuki Mizuno ,  Naoya Okubo

发明人： Hiroyuki Mizuno ,  Naoya Okubo

IPC分类号： F02D45/00 ,  G01M15/04

CPC分类号： G01D1/12

摘要： A control system for an internal combustion engine includes: a fuel amount detector; a smoothing calculation unit that calculates a smooth output value, which is obtained by smoothing an output value of the fuel amount detector in a temporal direction; a continuous low speed condition detection unit that detects a continuous low speed condition in which the vehicle speed remains in the low speed region continuously beyond a predetermined time period; a calculation processing unit that successively calculates a maximum value and a minimum value of the smooth output value; a reference setting unit that updates and stores a reference value in response to the engine stoppage and in accordance with the current minimum value calculated by the calculation processing unit; and a fuel supply determination unit that detects a fuel supply to the fuel tank during the continuous low speed condition.

摘要翻译： 一种用于内燃机的控制系统包括：燃料量检测器; 平滑计算单元，其计算通过在时间方向平滑所述燃料量检测器的输出值而获得的平滑输出值; 连续低速状态检测单元，其连续地检测所述车速保持在所述低速区域中的连续低速状态，超过预定时间段; 计算处理单元，其连续地计算平滑输出值的最大值和最小值; 参考设定单元，其根据所述发动机停止并根据由所述计算处理单元计算出的当前最小值来更新并存储基准值; 以及燃料供给确定单元，其在连续低速状态期间检测到燃料箱的燃料供给。

公开(公告)号：US07610572B2

公开(公告)日：2009-10-27

申请号：US11447168

申请日：2006-06-06

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

IPC分类号： G06F17/50 ,  H01L25/00

CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

摘要翻译： 一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。 在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。 还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

公开(公告)号：US07475261B2

公开(公告)日：2009-01-06

申请号：US10768136

申请日：2004-02-02

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07427791B2

公开(公告)日：2008-09-23

申请号：US11118951

申请日：2005-05-02

申请人： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

发明人： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

IPC分类号： H01L29/72

CPC分类号： H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

摘要翻译： 半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。 这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。 多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。 该控制电路插入在主电路和两个电源单元中的至少一个之间。

公开(公告)号：US07397053B2

公开(公告)日：2008-07-08

申请号：US11260254

申请日：2005-10-28

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： H01J49/00

CPC分类号： H01J37/3026 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  H01J37/3174 ,  H01J2237/31776

摘要： An electron beam control method has the following steps, selecting one of a plurality of pattern openings by a character beam electrode having a plurality of electrode units to allow an electron beam to pass through any pattern opening on an aperture mask on which the plurality of pattern openings are formed, determining whether or not a synchronization error of deflected operation of the electron beam performed by the plurality of electrode units is equal to or less than a tolerance, determining whether or not the electron beam is irradiated with a sample by selecting the pattern openings in sequence by the character beam electrode in a state of controlling a path of the electron beam by a blanking electrode not to irradiate the sample with the electron beam, when determined that the synchronization error is equal to or less than the tolerance, and decreasing the tolerance when determined that the electron beam is irradiated with the sample.

摘要翻译： 电子束控制方法具有以下步骤：通过具有多个电极单元的字符电极来选择多个图形开口中的一个，以允许电子束通过孔径掩模上的多个图案 形成开口，确定多个电极单元执行的电子束的偏转操作的同步误差是否等于或小于公差，通过选择图案来确定电子束是否被照射样品 当确定同步误差等于或小于公差时，通过字符光束电极在由控制不用电子束照射样品的消隐电极的电子束的路径的状态下依次进行开口，并且减小 当确定电子束被照射样品时的公差。

公开(公告)号：US20080138527A1

公开(公告)日：2008-06-12

申请号：US11907379

申请日：2007-10-11

申请人： Koji Okuma ,  Hiroyuki Mizuno

发明人： Koji Okuma ,  Hiroyuki Mizuno

IPC分类号： B05D3/02 ,  C08G63/91

CPC分类号： C09D161/28 ,  B05D7/577 ,  C08L61/28 ,  C08L63/00 ,  C08L67/02 ,  C08L2205/03 ,  C09D167/02 ,  C08L2666/14 ,  C08L2666/22 ,  C08L2666/18

摘要： The present invention relates to an intermediate coating composition, which comprises (a) a polyester resin comprising a polyester resin (i) and a polyester resin (ii), (b) a bisphenol type epoxy resin, and (c) an imino group-containing melamine resin, each of which contents of the components (a), (b) and (c) is relative to weight of the resin solid contents in the composition, wherein a weight ratio of the polyester resin (a)/the imino group-containing melamine resin (c) [(a)/(c)] is within a range of 50/50 to 70/30. Therefore, the present invention can provide an intermediate coating composition which can form a multi layered coating film having an excellent chipping resistance, as well as, a method for producing a multi layered coating film by using the intermediate coating composition.

摘要翻译： 本发明涉及一种中间涂料组合物，其包含（a）包含聚酯树脂（i）和聚酯树脂（ii）的聚酯树脂，（b）双酚型环氧树脂，和（c）亚氨基 - （a），（b）和（c）的含量相对于组合物中树脂固体成分的重量，其中聚酯树脂（a）/亚氨基的重量比 （c）[（a）/（c）]在50/50〜70/30的范围内。 因此，本发明可以提供能够形成耐崩裂性优异的多层涂膜的中间涂料组合物，以及使用中间涂料组合物制造多层涂膜的方法。

公开(公告)号：US20080116934A1

公开(公告)日：2008-05-22

申请号：US11970370

申请日：2008-01-07

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

IPC分类号： H03K3/01

CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

摘要： A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

摘要翻译： 一种半导体器件，包括具有多个反相器的频率可变振荡电路，每个反相器具有PMOS晶体管和NMOS晶体管，第一衬底偏置发生器包括第一相位/频率比较电路，其比较来自频率变量 具有参考时钟信号的振荡电路，并响应于此产生第一衬底偏置电压，第一衬底偏置电压被提供给振荡电路中的PMOS晶体管的衬底，第二衬底偏置发生器包括第二相/频率比较电路 其将来自频率可变振荡电路的输出信号与参考时钟进行比较，并响应于此产生第二衬底偏置电压，第二衬底偏置电压被提供给振荡电路中的NMOS晶体管的衬底。

公开(公告)号：US20080016383A1

公开(公告)日：2008-01-17

申请号：US11826854

申请日：2007-07-19

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

摘要翻译： 相反，当通过电源开关减小不使用状态下的电路块的漏电流时，短时间内开关频繁的接通/断开操作会引起消耗功率的增加。 由于开关的接通需要预热时间，直到电路块变得可用，所以在操作期间的开关的控制使半导体器件的处理时间变差。 该开关通过CPU核心的任务持续时间进行ON / OFF控制，用于将逻辑电路和存储器核心作为一个单元进行控制。 关闭开关后，考虑到预热时间，开关将在任务结束前再次打开。

公开(公告)号：US07254680B2

公开(公告)日：2007-08-07

申请号：US11641808

申请日：2006-12-20

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US20070063735A1

公开(公告)日：2007-03-22

申请号：US11526612

申请日：2006-09-26

申请人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

发明人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

IPC分类号： H03K19/0175

CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.

摘要翻译： 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。